9DMV0141 datasheet(6/10 Pages) IDT

6 / 10 page

2:1 1.8V PCIE GEN1-2-3 CLOCK MUX W/ZO=100OHMS

REVISION B 01/26/15

9DMV0141 DATASHEET

Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics

Electrical Characteristics–Phase Jitter Parameters

TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

NOTES

Duty Cycle Distortion

tDCD

Measured differentially, @100MHz

-1

-0.12

1,3

Skew, Input to Output

tpdBYP

VT = 50%

1853

2409

3132

Jitter, Cycle to cycle

tjcyc-cyc

Additive Jitter

0.1

1,2

1 Guaranteed by design and characterization, not 100% tested in production.

2 Measured from differential waveform

3 Duty cycle distortion is the difference in duty cycle between the output and the input clock.

TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

INDUSTRY

LIMIT

UNITS

Notes

tjphPCIeG1

PCIe Gen 1

1.3

N/A

ps (p-p) 1,2,3,5

PCIe Gen 2 Lo Band

10kHz < f < 1.5MHz

0.1

0.3

N/A

(rms)

1,2,3,4

PCIe Gen 2 High Band

1.5MHz < f < Nyquist (50MHz)

0.1

0.2

N/A

(rms)

1,2,3,4

tjphPCIeG3

PCIe Gen 3

(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)

0.065

0.1

N/A

(rms)

1,2,3,4

tjph125M0

125MHz, 1.5MHz to 10MHz, -20dB/decade

rollover < 1.5MHz, -40db/decade rolloff > 10MHz

284

350

N/A

(rms)

1,6

tjph125M1

125MHz, 12KHz to 20MHz, -20dB/decade

rollover < 12kHz, -40db/decade rolloff > 20MHz

420

500

N/A

(rms)

1,6

1Guaranteed by design and characterization, not 100% tested in production.

4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]

5 Driven by 9FGV0831 or equivalent

6 Driven by Rohde& Schartz SMA100

2 See http://www.pcisig.com for complete specs

3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.

Additive Phase Jitter,

Bypass Mode

tjphPCIeG2

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