PIC16C770-04SLASHSS datasheet(66/200 Pages) MICROCHIP

66 / 200 page

PIC16C717/770/771

DS41120A-page 66

Advanced Information

8.3.7

SYSTEM IMPLEMENTATION

When the ECCP module is used in the PWM mode, the

application hardware must use the proper external pull-

up and/or pull-down resistors on the PWM output pins.

When the microcontroller powers up, all of the I/O pins

are in the high-impedance state. The external pull-up

and pull-down resistors must keep the power switch

devices in the off state until the microcontroller drives

the I/O pins with the proper signal levels, or activates

the PWM output(s).

8.3.8

START-UP CONSIDERATIONS

Prior to enabling the PWM outputs, the P1A, P1B, P1C

and P1D latches may not be in the proper states.

Enabling the TRISB bits for output at the same time

with the CCP module may cause damage to the power

switch devices. The CCP1 module must be enabled in

the proper output mode with the TRISB bits enabled as

inputs. Once the CCP1 completes a full PWM cycle, the

P1A, P1B, P1C and P1D output latches are properly

initialized. At this time, the TRISB bits can be enabled

for outputs to start driving the power switch devices.

The completion of a full PWM cycle is indicated by the

TMR2IF bit going from a ’0’ to a ’1’.

8.3.9

SET UP FOR PWM OPERATION

The following steps should be taken when configuring

the ECCP module for PWM operation:

Configure the PWM module:

Disable the CCP1/P1A, P1B, P1C and/or

P1D outputs by setting the respective

TRISB bits.

Set the PWM period by loading the PR2

Set the PWM duty cycle by loading the

CCPR1L register and CCP1CON<5:4>

bits.

Configure the ECCP module for the desired

PWM operation by loading the CCP1CON

the active high/low levels for each PWM

output. With the PWM1M<1:0> bits select

one of the available output modes: Single,

Half-Bridge, Full-Bridge, Forward or Full-

Bridge Reverse.

For Half-Bridge output mode, set the dead-

band delay by loading the P1DEL register.

Configure and start TMR2:

Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit in the PIR1 register.

Set the TMR2 prescale value by loading the

T2CKPS<1:0> bits in the T2CON register.

Enable Timer2 by setting the TMR2ON bit

in the T2CON register.

Enable PWM outputs after a new cycle has

started:

Wait until TMR2 overflows (TMR2IF bit

becomes a ’1’). The new PWM cycle begins

here.

Enable the CCP1/P1A, P1B, P1C and/or

P1D pin outputs by clearing the respective

TRISB bits.

TABLE 8-3:

REGISTERS ASSOCIATED WITH PWM

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh, 8Bh,

10Bh,

18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000u

0Ch

PIR1

—

ADIF

—

SSPIF

CCP1IF

TMR2IF

TMR1IF

-0-- 0000

8Ch

PIE1

—

ADIE

—

SSPIE

CCP1IE

TMR2IE

TMR1IE

-0-- 0000

86h, 186h

TRISB

PORTB Data Direction Register

1111 1111

11h

TMR2

Timer2 register

0000 0000

92h

PR2

Timer2 period register

1111 1111

12h

T2CON

—

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

-000 0000

15h

CCPR1L

Capture/Compare/PWM register1 (LSB)

xxxx xxxx

uuuu uuuu

17h

CCP1CON

PWM1M1

PWM1M0

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

0000 0000

97h

P1DEL

PWM1 Delay value

0000 0000

Legend:

x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

PIC16C770-04/SS Datasheet(PDF) 66 Page - Microchip Technology

PIC16C770-04/SS Datasheet(HTML) 66 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL