PIC16C770-04SLASHSS datasheet(84/200 Pages) MICROCHIP

84 / 200 page

PIC16C717/770/771

DS41120A-page 84

Advanced Information

9.2.3

SLEEP OPERATION

While in sleep mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs, wake the processor from

sleep (if the SSP interrupt bit is enabled).

9.2.4

EFFECTS OF A RESET

A reset disables the MSSP module and terminates the

current transfer.

9.2.5

MASTER MODE

Master mode operation is supported by interrupt gen-

eration on the detection of the START and STOP con-

ditions. The STOP (P) and START (S) bits are cleared

from a reset or when the MSSP module is disabled.

Control of the I2C bus may be taken when the P bit is

set, or the bus is idle with both the S and P bits clear.

In master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

FIGURE 9-14: MSSP BLOCK DIAGRAM (I

2C MASTER MODE)

Read

Write

SSPSR

Start bit, Stop bit,

Start bit detect,

SSPBUF

Internal

Data Bus

Set/Reset, S, P, WCOL (SSPSTAT)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

Stop bit detect

Write collision detect

Clock Arbitration

State counter for

end of XMIT/RCV

SCL

SCL in

Bus Collision

SDA in

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM<3:0>,

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