PIC17C752-08SLASHCL datasheet(194/328 Pages) MICROCHIP

194 / 328 page

PIC17C7XX

DS30289A-page 194

17.6

In-Circuit Serial Programming

The PIC17C7XX group of the high end family

(PIC17CXXX) has an added feature that allows serial

programming while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent ﬁrmware or a custom ﬁrm-

ware to be programmed.

Devices may be serialized to make the product unique,

“special” variants of the product may be offered, and

code updates are possible. This allows for increased

design ﬂexibility.

To place the device into the serial programming test

mode, two pins will need to be placed at VIHH. These

are the TEST pin and the MCLR/VPP pin. Also a

sequence of events must occur as follows:

The TEST pin is placed at VIHH.

The MCLR/VPP pin is placed at VIHH.

There is a setup time between step 1 and step 2 that

must be met.

After this sequence the Program Counter is pointing to

program memory address 0xFF60. This location is in

the Boot ROM. The code initializes the USART/SCI so

that it can receive commands. For this, the device must

be clocked. The device clock source in this mode is the

RA1/T0CKI pin. After delaying to allow the USART/SCI

to initialize, commands can be received. The ﬂow is

shown in these 3 steps:

The device clock source starts.

Wait 80 device clocks for Boot ROM code to con-

ﬁgure the USART/SCI.

Commands may now be sent.

For complete details of serial programming, please

refer to the PIC17C7XX Programming Speciﬁcation.

(Contact your local Microchip Technology Sales Ofﬁce

for availability.)

FIGURE 17-4: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC17C7XX

VDD

VSS

MCLR/VPP

RA1/T0CKI

RA4/RX1/DT1

+5V

VPP

Dev. CLK

Data I/O

VDD

RA5/TX1/CK1

Data CLK

TEST

TEST CNTL

TABLE 17-3:

ICSP INTERFACE PINS

During Programming

Name

Function

Type

Description

RA4/RX1/DT1

I/O

Serial Data

RA5/TX1/CK1

Serial Clock

RA1/T0CKI

OSCI

Device Clock Source

TEST

Test mode selection control input. Force to VIHH,

MCLR/VPP

Master Clear reset and Device Programming Voltage

VDD

Positive supply for logic and I/O pins

VSS

Ground reference for logic and I/O pins

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