PIC18LC242-ESLASHP datasheet(47/296 Pages) MICROCHIP

47 / 296 page

PIC18CXX2

Preliminary

DS39026B-page 47

4.11

Bank Select Register (BSR)

The need for a large general purpose memory space

dictates a RAM banking scheme. The data memory is

partitioned into sixteen banks.

When using direct

addressing, the BSR should be configured for the

desired bank.

BSR<3:0> holds the upper 4 bits of the 12-bit RAM

address. The BSR<7:4> bits will always read ’0’s, and

writes will have no effect.

MOVLB instruction has been provided in the instruc-

tion set to assist in selecting banks.

If the currently selected bank is not implemented, any

read will return all '0's and all writes are ignored. The

STATUS register bits will be set/cleared as appropriate

for the instruction performed.

Each Bank extends up to FFh (256 bytes). All data

memory is implemented as static RAM.

A MOVFF instruction ignores the BSR, since the 12-bit

addresses are embedded into the instruction word.

Section 4.12 provides a description of indirect address-

ing, which allows linear addressing of the entire RAM

space.

FIGURE 4-8:

DIRECT ADDRESSING

Note 1: For register file map detail, see Table 4-1.

2: The access bit of the instruction can be used to force an override of the selected bank

(BSR<3:0>) to the registers of the Access Bank.

3: The MOVFF instruction embeds the entire 12-bit address in the instruction.

Data

Memory(1)

Direct Addressing

bank select

(2)

location select

(3)

BSR<3:0>

from opcode

(3)

00h

01h

0Eh

0Fh

Bank 0

Bank 1

Bank 14

Bank 15

1FFh

100h

0FFh

000h

EFFh

E00h

FFFh

F00h

PIC18LC242-E/P Datasheet(PDF) 47 Page - Microchip Technology

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