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ML2721 Datasheet(PDF) 19 Page - Micro Linear Corporation |
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ML2721 Datasheet(HTML) 19 Page - Micro Linear Corporation |
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19 / 27 page ![]() ML2721 19 January, 2000 PRELIMINARY DATASHEET PRELIMINARY Table 9C. Register 2 — Filter Tuning Select and Test Mode Register t i B a t a De m a Nn o i t p i r c s e De s U 3 1 B D / ) B S M ( 5 1 BE D O M Tt i B t c e l e S r e t l i f e n u Tn o i t a r e p O l a m r o N r o f 0 o t E D O M T t e S 2 1 B D / 4 1 Bd e v r e s e R ) o r e z ( 0 o t s t i B l l A t e S 1 1 B D / 3 1 Bd e v r e s e R 0 1 B D / 2 1 Bd e v r e s e R 9 B D / 1 1 Bd e v r e s e R 8 B D / 0 1 Bd e v r e s e R 7 B D / 9 Bd e v r e s e R 6 B D / 8 Bd e v r e s e R 5 B D / 7 B2 M T D s t i B l o r t n o C t s e T l a t i g i D3 1 e l b a T e e S 4 B D / 6 B1 M T D 3 B D / 5 B0 M T D 2 B D / 4 B2 M T A s t i B l o r t n o C t s e T g o l a n A2 1 e l b a T e e S 1 B D / 3 B1 M T A 0 B D / 2 B0 M T A 1 B D A / 1 B1 R D At i B s e e r d d A B S M1 = 1 R D A 0 B D A / ) B S L ( 0 B0 R D At i B s e e r d d A B S L0 = 0 R D A Figure 9. Serial Bus Timing for Address and Data Programming CLK tS DATA LSB EN tR tF tH tW tCK tSE tD MSB DB13 DB11 DB0 ADR1 ADR0 DB12 ADDRESS DATA (2 BITS) REGISTER DATA (14 BITS) CONTROL INTERFACES AND REGISTER DESCRIPTION (continued) Serial Interface Data and clock signals are ignored when EN is high. When EN is low data on the DATA pin is clocked into a shift register by rising edges on the CLK pin. The information is latched when EN goes high. This serial interface bus is similar to that commonly found on PLL devices. It can be efficiently programmed by either byte or 16-bit word oriented serial bus hardware. The data latches are implemented in static CMOS and use minimal power when the bus is inactive. Figure 9 and Table 10 provide timing and register programming illustrations. Table 10. 3-Wire Bus Timing Characteristics l o b m y Sr e t e m a r a P) s n ( e m i T t R e m i t e s i r t u p n i k c o l C5 1 t F 5 1 t K C 0 5 > t W h t d i w e s l u p m u m i n i M0 0 0 2 t D 5 1 > t E S 5 1 > t S 5 1 > t H e m i t d l o h k c o l c - o t - a t a D5 1 > |
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