ML2721 datasheet(7/27 Pages) MICRO-LINEAR

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ML2721

January, 2000

PRELIMINARY DATASHEET

PRELIMINARY

Mode Control and Interface Lines (Continued)

PLLEN

I (CMOS)

Enables the PLL at the beginning of a Transmit or Receive slot. Goes

low before data is received or transmitted. RXON and PLLEN define

four distinct operating modes. This is a CMOS input, and the thresholds

are referenced to VDD & VSS

LD/TPQ

O (CMOS)

The Lock Detect output is an open drain output that goes low when the

PLL is in frequency lock. In analog test modes this pin and the RSSI

output become test access points controlled by the serial control bus

REF

Input for the 6.144MHz or 12.288MHz reference frequency. This is

used as the reference frequency for the PLL, and as a calibration

frequency for the on chip filters. This is a self-biased CMOS input that

is designed to be driven either by a an AC coupled sine wave source

(recommended coupling capacitor is 470pF) or by a standard CMOS

output

QPO

Charge Pump Output of the phase detector. This is connected to the

external PLL loop filter

VTUNE

VCO Tuning Voltage input from the PLL loop filter. This pin is very

sensitive to noise coupling and leakage currents

VBG

Bandgap reference voltage. Decoupled to ground with a 220nF

capacitor

RSSI/TPI

Buffered Analog RSSI output with a nominal sensitivity of 33mV/dB.

An RF input signal range of –95 to –15dBm gives an RSSI voltage

output of zero to 2.7V. In analog test modes this pin and the LD output

become test access ports

Serial Bus Signals

I (CMOS)

Enable pin for the three wire serial control bus which sets the

operating frequency and programmable options. The control registers

are loaded on a low to high transition of the signal. Serial control bus

data is ignored when it is high. This is a CMOS input, and the

thresholds are referenced to VDD & VSS

DATA

I (CMOS)

Serial control bus data. 16 bit words which include programming data

and the two bit address of a control register. This is a CMOS input, and

the thresholds are referenced to VDD & VSS

CLK

I (CMOS)

Serial control bus data is clocked in on the rising edge when EN is

low. This is a CMOS input, the thresholds are referenced to VDD & VSS

PIN DESCRIPTIONS (continued)

Pin #

Signal Name

I/O

Description

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