LMZ12003EXT

SNVS663H – JUNE 2010 – REVISED AUGUST 2015

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9 Power Supply Recommendations

The LMZ12003EXT device is designed to operate from an input voltage supply range between 4.5 V and 20 V.

This input supply must be well regulated and able to withstand maximum input current and maintain a stable

voltage. The resistance of the input supply rail must be low enough that an input current transient does not cause

a high enough drop at the LMZ12003EXT supply voltage that can cause a false UVLO fault triggering and

system reset. If the input supply is more than a few inches from the LMZ12003EXT, additional bulk capacitance

may be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, but

a 47-

μF or 100-μF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout Guidelines

PCB layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a

DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop in

the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.

Good layout can be implemented by following a few simple design rules.

1. Minimize area of switched current loops.

From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths during PCB layout.

The high current loops that do not overlap have high di/dt content that will cause observable high frequency

minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the input and output

capacitor must consist of a localized top side plane that connects to the GND exposed pad (EP).

2. Have a single point ground.

The ground connections for the feedback, soft-start, and enable components must be routed to the GND pin

of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not

properly handled, poor grounding can result in degraded load regulation or erratic output voltage ripple

behavior. Provide the single point ground connection from pin 4 to EP.

3. Minimize trace length to the FB pin.

pin. Because the FB node is high impedance, maintain the copper area as small as possible. The trace are

4. Make input and output bus connections as wide as possible.

This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize

voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made to the load. Doing

so will correct for voltage drops and provide optimum output accuracy.

5. Provide adequate device heat-sinking.

Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer.

If the PCB has a plurality of copper layers, these thermal vias can also be employed to make connection to

inner layer heat-spreading ground planes. For best results use a 6 × 6 via array with minimum via diameter

of 8 mils thermal vias spaced 59 mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep

the junction temperature below 125°C.

18

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