AR0130CSSC00SPBA0-DP datasheet(18/53 Pages) ONSEMI

18 / 53 page

AR0130 DS Rev. L Pub. 6/15 EN

©Semiconductor Components Industries, LLC, 2015.

AR0130: 1/3-Inch CMOS Digital Image Sensor

Features

PLL-Generated Master Clock

The PLL contains a prescaler to divide the input clock applied on EXTCLK, a VCO to

multiply the prescaler output, and two divider stages to generate the output clock. The

clocking structure is shown in Figure 12. PLL control registers can be programmed to

generate desired master clock frequency.

Note:

The PLL control registers must be programmed while the sensor is in the software

Standby state. The effect of programming the PLL divisors while the sensor is in the

streaming state is undefined.

Figure 12:

PLL-Generated Master Clock PLL Setup

The PLL is enabled by default on the AR0130.

To Configure and Use the PLL:

1. Bring the AR0130 up as normal; make sure that fEXTCLK is between 6 and 50MHz and

ensure the sensor is in software standby (R0x301A[2]= 0). PLL control registers must

be set in software standby.

2. Set pll_multiplier, pre_pll_clk_div, vt_sys_clk_div, and vt_pix_clk_div based on the

desired input (fEXTCLK) and output (fPIXCLK) frequencies. Determine the M, N, P1, and

P2 values to achieve the desired fPIXCLK using this formula:

fPIXCLK= (fEXTCLK × M) / (N × P1 x P2)

where

M = PLL_Multiplier (R0x3030)

N = Pre_PLL_Clk_Div (R0x302E)

P1 = Vt_Sys_Clk_Div (R0x302C)

P2 = Vt_PIX_Clk_Div (R0x302A)

3. Wait 1ms to ensure that the VCO has locked.

4. Set R0x301A[2]=1 to enable streaming and to switch from EXTCLK to the PLL-gener-

ated clock.

Notes:

1. The PLL can be bypassed at any time (sensor will run directly off EXTCLK) by setting

R0x30B0[14]=1. However, only the parallel data interface is supported with the PLL

bypassed. The PLL is always bypassed in software standby mode. To disable the PLL,

the sensor must be in standby mode (R0x301A[2] = 0)

2. The following restrictions apply to the PLL tuning parameters:

Pre PLL

Div

(PFD)

Pre_pll_clk_div

EXTCLK

PLL

Multiplier

(VCO)

PLL Output

Div 1

SYSCLK

PIXCLK

vt_pix_clk_div

vt_sys_clk_div

PLL Input

Clock

PLL Output

Clock

PLL Output

Div 2

pll_multiplier

255

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1P116

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