KAI-08050 datasheet(25/31 Pages) ONSEMI

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KAI−08050

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Photodiode Transfer Timing

A row of charge is transferred to the HCCD on the falling

edge of V1 as indicated in the P1 pattern below. Using this

timing sequence, the leading dummy row or line is

combined with the first dark row in the HCCD. The “Last

Line” is dependent on readout mode – either 632 or 1264

minimum counts required. It is important to note that, in

general, the rising edge of a vertical clock (patterns P1−P4)

should be coincident or slightly leading a falling edge at the

same time interval. This is particularly true at the point

where P1 returns from the high (3rd level) state to the

mid−state when P4 transitions from the low state to the high

state.

Figure 20. Photodiode Transfer Timing

Last Line

L1 + Dummy Line

P1B

P2B

P3B

P4B

Pattern

P1T

P2T

P3T

P4T

tv/2

tpd

tv/2

t3p

t3d

ths

tv/2

ths

tv/2

1 2

5 6

Line and Pixel Timing

Each row of charge is transferred to the output, as

illustrated below, on the falling edge of H2SL (indicated as

P6 pattern). The number of pixels in a row is dependent on

readout mode – either 853 or 1706 minimum counts

required.

Figure 21. Line and Pixel Timing

P1T

Pixel

line

e/2

VOUT

Pattern

P1B

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