ACE25Q512G datasheet(21/42 Pages) ACE

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ACE25Q512G

512K BIT SPI NOR FLASH Memory Series

VER 1.1

Continuous Read Mode Reset (FFH or FFFFH)

The “Continuous Read Mode” bits are used in conjunction with “Fast Read Dual I/O” and “Fast

Read Quad I/O” Instructions to provide the highest random Flash memory access rate with minimum

SPI instruction overhead, thus allowing more efficient XIP (execute in place) with this device family.

The “Continuous Read Mode” bits M7-0 are set by the Dual/Quad I/O Read Instructions. M5-4 are

used to control whether the 8-bit SPI instruction code (BBH or EBH) is needed or not for the next

instruction. When M5-4 = (1,0), the next instruction will be treated the same as the current Dual/Quad

I/O Read instruction without needing the 8-bit instruction code; when M5-4 do not equal to (1,0), the

device returns to normal SPI instruction mode, in which all instructions can be accepted. M7-6 and

M3-0 are reserved bits for future use, either 0 or 1 values can be used.

Figure 15 the Continuous Read Mode Reset instruction (FFH or FFFFH) can be used to set M4 = 1,

thus the device will release the Continuous Read Mode and return to normal SPI operation.

To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. The

instruction is “FFH”. To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are

needed to shift in instruction “FFFFH

Figure 15 Continuous Read Mode Reset Sequence Diagram

Figure 15

ACE25Q512G Datasheet(PDF) 21 Page - ACE Technology Co., LTD.