TMP112-Q1

SLOS887D – SEPTEMBER 2014 – REVISED DECEMBER 2015

www.ti.com

7.3.2.4 Slave Mode Operation

The TMP112-Q1 device can operate as a slave receiver or slave transmitter. As a slave device, the TMP112-Q1

device never drives the SCL line.

7.3.2.4.1

Slave Receiver Mode

The first byte transmitted by the master is the slave address with the R/W bit low. The TMP112-Q1 device then

acknowledges reception of a valid address. The next byte transmitted by the master is the pointer register. The

TMP112-Q1 device then acknowledges reception of the pointer register byte. The next byte or bytes are written

to the register addressed by the pointer register. The TMP112-Q1 device acknowledges reception of each data

byte. The master can terminate data transfer by generating a START or STOP condition.

7.3.2.4.2

Slave Transmitter Mode

The first byte transmitted by the master is the slave address with the R/W bit high. The slave acknowledges

reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of

the register indicated by the pointer register. The master acknowledges reception of the data byte. The next byte

transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The

master can terminate data transfer by generating a not-acknowledge on reception of any data byte or by

generating a START or STOP condition.

7.3.2.5 SMBus Alert Function

The TMP112-Q1 device supports the SMBus alert function. When the TMP112-Q1 device operates in interrupt

mode (TM = 1), the ALERT pin can be connected as an SMBus alert signal. When a master senses that an alert

condition is present on the alert line, the master sends an SMBus ALERT command (0001 1001) to the bus. If

the ALERT pin is active, the device acknowledges the SMBus ALERT command and responds by returning the

slave address on the SDA line. The eighth bit (LSB) of the slave address byte indicates if the alert condition is

If multiple devices on the bus respond to the SMBus ALERT command, arbitration during the slave address

portion of the SMBus ALERT command determines which device clears the alert status of that device. The

device with the lowest two-wire address wins the arbitration. If the TMP112-Q1 device wins the arbitration, the

TMP112-Q1 ALERT pin becomes inactive at the completion of the SMBus ALERT command. If the TMP112-Q1

device loses the arbitration, the TMP112-Q1 ALERT pin remains active.

7.3.2.6 General Call

The TMP112-Q1 device responds to a two-wire general-call address (0000 000) if the eighth bit is 0. The device

acknowledges the general-call address and responds to commands in the second byte. If the second byte is

0000 0110, the TMP112-Q1 internal registers are reset to power-up values. The TMP112-Q1 device does not

support the general-address acquire command.

7.3.2.7 High-Speed (Hs) Mode

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an Hs-mode

master code (0000 1xxx) as the first byte after a START condition to switch the bus to high-speed operation. The

TMP112-Q1 device does not acknowledge this byte, but switches the input filters on the SDA and SCL pins and

the output filters on the SDA pin to operate in Hs-mode thus allowing transfers at up to 2.85 MHz. After the Hs-

mode master code has been issued, the master transmits a two-wire slave address to initiate a data-transfer

operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving

the STOP condition, the TMP112-Q1 device switches the input and output filters back to fast-mode operation.

7.3.2.8 Timeout Function

The TMP112-Q1 device resets the serial interface if the SCL pin is held low for 30 ms (typical) between a start

and stop condition. The TMP112-Q1 releases the SDA line if the SCL pin is pulled low and waits for a start

condition from the host controller. To avoid activating the timeout function, maintain a communication speed of at

least 1 kHz for SCL operating frequency.

12

Submit Documentation Feedback

Copyright © 2014–2015, Texas Instruments Incorporated

Product Folder Links: TMP112-Q1