SM5906AF datasheet(24/30 Pages) NPC

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NIPPON PRECISION CIRCUITS-24

SM5906AF

– DRAM initialization refresh

An 8-cycle RAS-only refresh is carried out for

DRAM initialization under the following conditions.

When MSON changes from 0 to 1 using command

80H.

When

from

MSON=1,

MSRDEN=0

and

MSWREN=0 states only MSWREN changes to 1.

In this case, write sequence immediately starts and

initial data is written (at 2fs rate input) after a delay

of 50

µs.

– Refresh during Shock-proof mode operation

In this IC, a data access operation to any address

also serves as a data refresh.

A data access to DRAM can occur in an write

sequence write operation or in a read sequence

read operation. Write sequence write operation

stops during a connect operation whereas a read

sequence read operation always continues while

data is output to the D/A. The refresh rate for each

DRAM during read sequence is shown in the table

below.

The read sequence, set by MSON=1 and MSR-

DEN=1, operates when valid data is in DRAM

(when MSEMP=0).

– When MSON=0, DRAM is not refreshed because

no data is being accessed. Although MSON=1,

DRAM is not refreshed if ENCOD=0 and DECOD=0

(both encode and decode sequence are stopped).

DRAM refresh

Table 2. Read sequence refresh rate

DRAMs used

Data compression mode

4M (1M

×4 bits)

16M(4M

×4 bits)

CDDA mode

2.91 ms

5.81 ms

VCD mode

2.58 ms

5.17 ms

SVC mode

1.29 ms

2.59 ms

Write sequence temporary stop

– When RAM becomes full, MSWREN is set LOW

using the 80H command and write sequence stops.

(For details of the stop conditions, refer to the

description of the WASQ flag.)

– Then, if MSWREN is set HIGH without issuing a

compare-connect start command, the write

sequence re-starts. At this time, new input data is

written not to VWA, but to WA. In this way, the data

already written to the region between VWA and WA

is not lost.

– But if the MSWREN is set HIGH (80H command)

after using the compare-connect start command

even only once, data is written to VWA. If data is

input before comparison and conformance is

detected, the same operation as direct-connect

mode takes place when the command is issued.

After comparison and conformance are detected,

no operation is performed because the write

sequence has already been started. However,

make sure that the other bit settings within the

same 80H command are valid.

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