PIC16LF72SLASHP datasheet(47/136 Pages) MICROCHIP

47 / 136 page

 2002 Microchip Technology Inc.

DS39597B-page 45

PIC16F72

SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

= The SSPBUF register is written while it is still transmitting the previous word (must be

cleared in software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

In SPI mode:

= A new byte is received while the SSPBUF register is still holding the previous data. In case

of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user

must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master

mode, the overflow bit is not set since each new reception (and transmission) is initiated

by writing to the SSPBUF register.

= No overflow

In I2C mode:

= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV

is a "don’t care" in Transmit mode. SSPOV must be cleared in software in either mode.

= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In SPI mode:

= Enables serial port and configures SCK, SDO, and SDI as serial port pins

= Disables serial port and configures these pins as I/O port pins

In I2C mode:

= Enables the serial port and configures the SDA and SCL pins as serial port pins

= Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

= IDLE state for clock is a high level (Microwire® default)

= IDLE state for clock is a low level (Microwire alternate)

In I2C mode:

SCK release control

= Enable clock

= Holds clock low (clock stretch - used to ensure data setup time)

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000

= SPI Master mode, clock = FOSC/4

0001

= SPI Master mode, clock = FOSC/16

0010

= SPI Master mode, clock = FOSC/64

0011

= SPI Master mode, clock = TMR2 output/2

0100

= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101

= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

0110

=I2C Slave mode, 7-bit address

0111

=I2C Slave mode, 10-bit address

1011

=I2C firmware controlled Master mode (Slave IDLE)

1110

=I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1111

=I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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