7

Rev.1.0

28 -

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memory area which is read-only and unalterable.

Deep Power-Down Mode command.

Status Register Content

Memory Content

BP2

BP1

BP0

Blocks

Addresses

Density

Portion

0

0

0

NONE

NONE

NONE

NONE

0

0

1

Sector 0 to 29

000000H-01DFFFH

120KB

Lower 30/32

0

1

0

Sector 0 to 27

000000H-01BFFFH

112KB

Lower 28/32

0

1

1

Sector 0 to 23

000000H-017FFFH

96KB

Lower 24/32

1

0

0

Sector 0 to 15

000000H-00FFFFH

64KB

Lower 16/32

1

0

1

All

000000H-01FFFFH

128KB

All

1

1

×

All

000000H-01FFFFH

128KB

All

Table 1. GD25D10B Protected area size

6. STATUS REGISTER

The status and control bits of the Status Register are as follows:

WIP bit.

The Write In Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register

progress. When WIP bit is set to 1, it means the device is busy in program/erase/write status register progress.

When WIP bit is cleared to 0, it means the device is not in program/erase/write status register progress. The

default value of WIP is 0.

WEL bit.

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the

internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no write Status

Register, Program or Erase command is accepted. The default value of WEL is 0.

BP2, BP1, BP0 bits.

The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Statue Register (WRSR)

command. When the Block Protect (BP2, BP1, BP0) bits are set to 1, the relevant memory area (as defined in

Table1). Becomes protected against Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands.

S7

S6

S5

S4

S3

S2

S1

S0

SRP

Reserved

Reserved

BP2

BP1

BP0

WEL

WIP