FS7140, FS7145

http://onsemi.com

8

SYNC Circuitry

The FS7145 supports nearly instantaneous adjustment of

the output CLK phase by the SYNC input. Either edge

direction of SYNC (positive−going or negative−going) is

supported.

Example (positive−going SYNC selected): Upon the

negative edge of SYNC input, a sequence begins to stop the

CLK output. Upon the positive edge, CLK resumes

operation, synchronized to the phase of the SYNC input

(plus a deterministic delay). This is performed by control of

the device post−divider. Phase resolution equal to 1/2 of the

VCO period can be achieved (approximately down to 2 ns).

This device is a read/write slave device meeting all Philips

to be controlled by a master device that generates the serial

clock SCL, controls bus access and generates the START

and STOP conditions while the device works as a slave. Both

master and slave can operate as a transmitter or receiver, but

the master device determines which mode is activated. A

device that sends data onto the bus is defined as the

transmitter, and a device receiving data as the receiver.

Bus Conditions

Data transfer on the bus can only be initiated when the bus

is not busy. During the data transfer, the data line (SDA)

must remain stable whenever the clock line (SCL) is high.

Changes in the data line while the clock line is high will be

interpreted by the device as a START or STOP condition.

protocol.

Not Busy

Both the data (SDA) and clock (SCL) lines remain high to

indicate the bus is not busy.

START Data Transfer

A high to low transition of the SDA line while the SCL

input is high indicates a START condition. All commands to

the device must be preceded by a START condition.

STOP Data Transfer

A low to high transition of the SDA line while SCL input

is high indicates a STOP condition. All commands to the

device must be followed by a STOP condition.

Data Valid

The state of the SDA line represents valid data if the SDA

line is stable for the duration of the high period of the SCL

line after a START condition occurs. The data on the SDA

line must be changed only during the low period of the SCL

signal. There is one clock pulse per data bit.

Each data transfer is initiated by a START condition and

terminated with a STOP condition. The number of data bytes

transferred between START and STOP conditions is

determined by the master device, and can continue

indefinitely. However, data that is overwritten to the device

after the first eight bytes will overflow into the first register,

then the second, and so on, in a first−in, first−overwritten

fashion.

Acknowledge

When addressed, the receiving device is required to

generate an acknowledge after each byte is received. The

master device must generate an extra clock pulse to coincide

with the acknowledge bit. The acknowledging device must

pull the SDA line low during the high period of the master

acknowledge clock pulse. Setup and hold times must be

taken into account.

The master must signal an end of data to the slave by not

generating and acknowledge bit on the last byte that has been

read (clocked) out of the slave. In this case, the slave must

leave the SDA line high to enable the master to generate a

STOP condition.

All programmable registers can be accessed randomly or

sequentially via this bi−directional two wire digital

interface. The crystal oscillator does not have to run for

communication to occur.

Slave Address

After generating a START condition, the bus master

broadcasts a seven−bit slave address followed by a R/W bit.

The address of the device is:

A6

A5

A4

A3

A2

A1

A0

1

0

1

1

0

X

X

where X is controlled by the logic level at the ADDR pins.

The selectable ADDR bits allow four different FS7140

devices to exist on the same bus. Note that every device on

conflicts.

Random Register Write Procedure

Random write operations allow the master to directly

write to any register. To initiate a write procedure, the R/W

bit that is transmitted after the seven−bit device address is a

logic−low. This indicates to the addressed slave device that

a register address will follow after the slave device

acknowledges its device address. The register address is

written into the slave’s address pointer. Following an

acknowledge by the slave, the master is allowed to write

eight bits of data into the addressed register. A final

acknowledge is returned by the device, and the master

generates a STOP condition.