Z8018233FSC datasheet(70/109 Pages) ZILOG

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16550 MIMIC REGISTERS (Continued)

FIFO Control Register

Bit 6 and Bit 7 RCVR trigger LSB and MSB bits

This 2-bit field determines the number of available bytes in

the receiver FIFO before an interrupt to the PC occurs (see

Table 18).

Bit 4 and Bit 5

Reserved for future use (PC side). Note: From the MPU

side, bit 4 and bit 5 flags two sources of interrupts. Bit 5 is

a FIFO interrupt indicating that the FCR had changed; bit

4 is a Tx overrun interrupt, indicating transmit overrun. A

read of the FCR from the MCU side will clear a previously

set bit 4 or bit 5.

Bit 3 DMA mode select

Setting this bit to 1 will cause the MIMIC DMA mode to

change from mode 0 to mode 1 (if bit 0 is 1, FIFO mode is

enabled). This affects the DMA mode of the FIFO. A 1 in this

bit enables multi-byte DMA).

Bit 2 XMIT FIFO Reset

Setting this bit to 1 will cause the transmitter FIFO pointer

logic to be reset; any data in the FIFO will be lost. This bit

is self clearing; however a shadow bit exists that is cleared

only when read by the Z180 MPU, allowing the MPU to

monitor a FIFO reset by the PC.

Bit 1 RCVR FIFO Reset

Setting this bit to 1 will cause the receiver FIFO pointer

logic to be reset; any data in the FIFO will be lost. This bit

is self clearing, however a shadow bit exists that is cleared

only when read by the Z180 MPU, allowing the MPU to

monitor a FIFO reset by the PC.

Bit 0 FIFO Enable

The PC writes this bit to logic 1 to put the 16550 MIMIC into

FIFO mode. This bit must be 1 when writing to the other bits

in this register or they will not be programmed. When this

bit changes state, any data in the FIFO’s or transmitter

holding and Receive Buffer Registers is lost and any

pending interrupts are cleared. This feature can be forced

in a disabled state by the MPU.

Table 18. Receive Trigger Level

Trigger Level, Number of Bytes

000000

16550/450 RCVR Overrun

Fast Interrupt Resolution

Figure 72. MIMIC Modification Register

(Z180 MPU Write only, Address xxE9h)

Bit 7-2 Reserved. Program to zero.

Bit 1 RCVR Overrun Modification

The actual 16450/16550 device allows the last position in

FIFO to be overwritten by DCE during receiver overrun

condition. When this bit is enabled (programmed to 1) the

last position in FIFO can be overwritten by Z180 during

receiver overrun. This feature is disabled by default. When

this modification is not enabled, the MIMIC will ignore any

write to RBR during an overrun condition.

Bit 0 Fast MIMIC-ESCC Interrupt Resolution

When enabling this modification, the internal MIMIC IEO

signal into the ESCC IEI input is forced Low when the

MIMIC Interrupt line becomes active. This is required to

prevent the ESCC from putting it's vector on the databus

during an INTACK cycle (given that the MIMIC is

programmed to have higher interrupt priority).

When disabled, the internal MIMIC IEO becomes

deasserted only after an interrupt acknowledge cycle. In

this case, it is possible for the ESCC to force it's interrupt

vector onto the data bus even when the MIMIC has a

pending interrupt and is higher in priority.

Z8018233FSC Datasheet(PDF) 70 Page - Zilog, Inc.

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