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Z80C3010VSC Datasheet(PDF) 50 Page - Zilog, Inc. |
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Z80C3010VSC Datasheet(HTML) 50 Page - Zilog, Inc. |
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50 / 96 page ![]() =&=&&026 6&& 6HULDO &RPPXQLFDWLRQV &RQWUROOHU 36 )XQFWLRQDO'HVFULSWLRQ )LJXUH :ULWH5HJLVWHU%LW)XQFWLRQV Register 0 * 0 0 01 1 0 1 1 0 0 0 1 1 0 1 1 Null Code Null Code Null Code Null Code Null Code * B Channel Only Reset Rx CRC Checker Reset Tx CRC Checker Reset Tx Underrun/EOM Latch Reset Ext/Status Interrupts Send Abort Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS Select Shift Left Mode Select Shift Right Mode 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Write Register 0 (multiplexed bus mode) D7 D6 D5 D4 D3 D2 D1 D0 Write Register 0 (non-multiplexed bus mode) Null Code 0 0 0 1 1 0 1 1 * With Point High Command Reset Rx CRC Checker Reset Tx CRC Generator Reset Tx Underrun/EOM Latch Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 9 Register 10 Register 11 Register 12 Register 13 Register 14 Register 15 * 0 00 00 00 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 0 00 00 0 00 0 0 1 11 1 1 1 1 1 1 1 1 1 Null Code Point High Reset Ext/Status Interrupts Send Abort (SDLC) Enable Int on Next Rx Character Reset Tx Int Pending Error Reset Reset Highest IUS D7 D6 D5 D4 D3 D2 D1 D0 Write Register 1 0 0 0 0 1 1 1 1 Ext Int Enable Tx Int Enable Parity is Special Condition Rx Int on Special Condition Only Int on all Rx Characters or Special Condition Rx Int on First Character or Special Condition WAIT/DMA Request on Receive /Transmit Rx Int Disable WAIT/DMA Request Function WAIT/DMA Request D7 D6 D5 D4 D3 D2 D1 D0 Write Register 2 V0 V1 V2 V3 V4 V5 V6 V7 Interrupt Vector D7 D6 D5 D4 D3 D2 D1 D0 Write Register 3 Rx Enable Sync Character Load Inhibit Address Search Mode (SDLC) Rx CRC Enable Enter Hunt Mode Auto Enables 0 0 0 0 1 1 1 1 Rx 5 Bits/Character Rx 7 Bits/Character Rx 6 Bits/Character Rx 8 Bits/Character |
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