DLPC2607

DLPS030C – DECEMBER 2013 – REVISED NOVEMBER 2015

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Table of Contents

7.2

Functional Block Diagram ....................................... 19

1

Features .................................................................. 1

7.3

Feature Description................................................. 19

2

Applications ........................................................... 1

7.4

Programming........................................................... 21

3

Description ............................................................. 1

7.5

Device Functional Modes........................................ 22

4

Revision History..................................................... 2

8

Application and Implementation ........................ 23

5

Pin Configuration and Functions ......................... 3

8.1

Application Information............................................ 23

6

Specifications......................................................... 8

8.2

Typical Application ................................................. 23

6.1

Absolute Maximum Ratings ...................................... 8

9

Power Supply Recommendations ...................... 27

6.2

ESD Ratings.............................................................. 8

9.1

System Power Considerations ................................ 27

6.3

Recommended Operating Conditions ....................... 8

9.2

System Power-Up and Power-Down Sequence ..... 27

6.4

Thermal Information .................................................. 9

9.3

System Power I/O State Considerations ............... 29

6.5

Typical Current and Power Dissipation..................... 9

9.4

Power-Up Initialization Sequence ........................... 29

6.6

I/O Characteristics................................................... 10

9.5

Power-Good (PARK) Support ................................ 30

6.7

Internal Pullup and Pulldown Characteristics ........ 10

10

Layout................................................................... 31

6.8

Parallel I/F Frame Timing Requirements ................ 11

10.1

Layout Guidelines ................................................. 31

6.9

Parallel I/F General Timing Requirements.............. 11

10.2

Layout Example .................................................... 37

6.10

Parallel I/F Max Supported Horizontal Line Rate.. 12

11

Device and Documentation Support ................. 38

6.11

BT.565 I/F General Timing Requirements ............ 13

11.1

Device Support...................................................... 38

6.12

100- to 120-Hz Operational Limitations ................ 13

11.2

Community Resources.......................................... 39

6.13

Flash Interface Timing Requirements .................. 14

11.3

Trademarks ........................................................... 39

6.14

DMD Interface Timing Requirements ................... 14

11.4

Electrostatic Discharge Caution ............................ 39

6.15

mDDR Memory Interface Timing Requirements .. 15

11.5

Glossary ................................................................ 39

7

Detailed Description ............................................ 19

12

Mechanical, Packaging, and Orderable

7.1

Overview ................................................................. 19

Information ........................................................... 39

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (January 2014) to Revision C

Page

•

Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,

Application and Implementation section, Power Supply Recommendations section, Layout section, Device and

Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1

Changes from Revision A (December 2013) to Revision B

Page

•

Removed product preview banner.......................................................................................................................................... 1

Changes from Original (December 2013) to Revision A

Page

•

•

•

Added additional table notes to I/O Characteristics ............................................................................................................ 10

•

Added table note to Internal Pullup and Pulldown Characteristics ...................................................................................... 10

•

Corrected device reference to DLPC2607 in the notes for mDDR Memory Interface Timing Requirements ..................... 15

2

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