DLPC2607

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DLPS030C – DECEMBER 2013 – REVISED NOVEMBER 2015

Feature Description (continued)

To support 3-D operation, run the DLPC2607 device in Lock-to-VSYNC mode with 1× frame rate multiplication

(that is, no frame rate multiplication). Each DMD frame is displayed at the source frame rate in the order it is

received.

Because of the high frame rate of the source, the source line rate must be much higher than typical, but still

cannot exceed the rates defined in Parallel I/F Max Supported Horizontal Line Rate. The minimum line rate is

limited by the maximum frame rate and minimum total vertical blanking (TVB). 100- to 120-Hz Operational

Limitations provides a summary of the line rate range assuming the minimum TVB.

7.4 Programming

7.4.1 Serial Flash Interface

The DLPC2607 device uses an external SPI serial flash memory device for configuration support. The minimum

required size depends on the desired minimum number of sequences, CMT tables, and splash options while the

maximum supported is 16 Mb. Table 1 provides the list of the configuration options.

QUANTITY OF FEATURES THAT CAN BE SUPPORTED

TARGET

OPTICAL TEST

STANDARD

SERIES

DLP DISPLAY

FLASH

UNIT DATA ODM DATA

CMT TABLES PER

SPLASH

SPLASH

DATA

SEQUENCES

DENSITY (Mb)

SECTOR

SECTOR

SCREENS

SCREENS

SECTOR

(2)

4 Mb

0

1

1

1

1

16

7

8 Mb

0

3

1

1

1

16

7

16 Mb

1

4

1

1

1

16

7

(1)

All rows in this table have passed DVT at TI.

(2)

Assumes individual DLP display sequences are limited to 5 KB each

(3)

An equal number of CMT tables are required for each sequence (CMT tables define the DeGamma Curve). The DLPC2607 device uses

a single SPI, employing SPI mode 0 protocol, operating at a frequency of 33.3 MHz. It supports two independent SPI chip selects.

However, the primary flash must be connected to SPI chip select 0 (SPICS0) because the auto-initialization routine is always executed

from the device connected to this chip select. The auto-initialization routine executed from flash consists of the following:

(a) The DLPC2607 device first uploads the size and location of the auto-initialization routine from address range 0x0000 through 0x0007

of the serial flash memory connected to SPICS0.

(b) The DLPC2607 device then uploads the actual auto-initialization routine to its ICP program memory from the serial flash memory

connected to SPICS0.

(c) The DLPC2607 device then executes an auto-init routine, which includes uploading default control parameter values, uploading

mailbox memory contents, turning on the sequence and LEDs, and then enabling the display.

(d) Upon completion of the auto-initialization routine, the DLPC2607 signals INIT DONE with GPIO4_INTF.

The DLPC2607 device should support any flash device that is compatible with these modes of operation.

However, the DLPC2607 device does not support the Normal (slow) Read Opcode, and thus cannot

automatically adapt protocol and clock rate based on the flash’s electronic signature ID. The flash instead uses a

fixed SPI clock and assumes certain attributes of the flash have been ensured by PCB design. The DLPC2607

device also assumes the flash supports address auto-incrementing for all read operations. Table 2 and Table 3

list the specific instruction OpCode and timing compatibility requirements for a DLPC2607 device compatible

flash.

Table 2. SPI Flash Instruction OpCode and Timing Compatibility Requirements

SPI FLASH COMMAND

OPCODE (hex)

ADDRESS BYTES

DUMMY BYTES

MIN CLOCK RATE

Fast READ (single output)

0x0B

3

1

33.3 MHz

All others

Can vary

Can vary

Can vary

33.3 MHz

Table 3. SPI Flash Key Timing Parameter Compatibility Requirements

MIN

MAX

UNIT

Minimum chip select high time

300

ns

Minimum output hold time

0

ns

Maximum output valid time

9

ns

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