DLPC2607

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DLPS030C – DECEMBER 2013 – REVISED NOVEMBER 2015

6.11 BT.565 I/F General Timing Requirements

The DLPC2607 ASIC input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITU-

R BT.656 specification for detailed interface timing requirements. BT.656 data bits should be mapped to the DLPC2607

PDATA bus as shown in Figure 3.

(1)

MIN

MAX

UNIT

Clock frequency, PCLK

1

33.5

MHz

Clock period, PCLK

50% reference points

29.85

1000

ns

(2)

(2)

Pulse duration low, PCLK

50% reference points

10

ns

Pulse duration high, PCLK

50% reference points

10

ns

Setup time – HSYNC, DATEN, PDATA(23:0) valid

50% reference points

3

ns

before the active edge of PCLK

Hold time – HSYNC, DATEN, PDATA(23:0) valid

50% reference points

3

ns

after the active edge of PCLK

Transition time – All signals

20% to 80% reference points

0.2

4

ns

(1)

The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard though PDATA(7:0) on the active edge of

PCLK (that is, programmable) as shown in Figure 2.

(2)

6.12 100- to 120-Hz Operational Limitations

MIN FRAME

NOM FRAME MAX FRAME

MIN TVB

MAX LINE

MIN LINE

MIN CLOCK

RESOLUTION

SOURCE

RATE

RATE

RATE

(tp_tvb)

RATE

RATE

RATE

(APPL x ALPF)

(Hz)

(Hz)

(Hz)

(LINES)

(kHz)

(kHz)

(MHz)

nHD

640 × 360

99

100

101

12

48

(1)

(2)

WQVGA

427 × 240

99

100

101

12

32

(1)

(2)

QVGA

320 × 240

99

100

101

12

32

(1)

(2)

nHD

640 × 360

118.8

120

121.2

12

48

(1)

(2)

WQVGA

427 × 240

118.8

120

121.2

12

32

(1)

(2)

QVGA

320 × 240

118.8

120

121.2

12

32

(1)

(2)

(1)

Use the following equation to determine the minimum line rate for a given application. The application cannot be supported if the

calculated minimum line rate exceeds the maximum line rate defined elsewhere in this table;

Line_Rate_min (kHz) = Frame_Rate_max (Hz) × [ALPF + TVB] /1000

Where: TVB = Total vertical blanking (in lines)

ALPF = Active lines per frame

Frame_Rate_max = Max frame rate including all expected wander

(2)

The following equation should be used to determine the minimum pixel clock rate for a given application. The application cannot be

supported if the calculated minimum pixel clock rate exceeds the max pixel clock rate defined in Parallel I/F General Timing

Requirements.

Pixel_Clock_min (MHz) = Line_Rate_max (kHz) × (APPL + 12) / 1000

Where: APPL = Active pixels per line

Line_Rate_max = Max line rate including all expected wander

SPACE

NOTE

It is assumed that a front-end device ahead of the DLPC2607 device converts all 3-D

sources to the 3-D format defined previously and provides any needed left-eye or right-eye

selection control directly to the 3-D glasses (that is, the DLPC2607 device does not control

the glasses). Note that the DLPC2607 device includes a double buffer frame memory,

which causes the displayed image to be delayed one frame relative to its input. This

requires left or right eye-frame shutter control to be inverted prior to being sent to the

glasses.

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