CAP1133 datasheet(11/63 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001625B-page 11

CAP1133

4.2.5

SMBUS STOP BIT

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the

SMBus clock line is in a logic ‘1’ state. When the CAP1133 detects an SMBus Stop bit and it has been communicating

with the SMBus protocol, it will reset its slave interface and prepare to receive further communications.

4.2.6

SMBUS TIMEOUT

The CAP1133 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus where the

SMCLK pin is held low, the device will timeout and reset the SMBus interface.

The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the Configuration register

(see Section 6.6, "Configuration Registers").

4.2.7

SMBUS AND I2C COMPATIBILITY

The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus

2.0 and I2C specifications. For information on using the CAP1133 in an I2C system, refer to AN 14.0 Dedicated Slave

Devices in I2C Systems.

CAP1133 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz.

Minimum frequency for SMBus communications is 10kHz.

The SMBus slave protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout function-

ality is disabled by default in the CAP1133 and can be enabled by writing to the TIMEOUT bit. I2C does not have

a timeout.

The SMBus slave protocol will reset if both the clock and data lines are held at a logic ‘1’ for longer than 200µs

(idle condition). This function is disabled by default in the CAP1133 and can be enabled by writing to the TIME-

OUT bit. I2C does not have an idle condition.

I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).

I2C devices support block read and write differently. I2C protocol allows for unlimited number of bytes to be sent

in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read /

write is transmitted. The CAP1133 supports I2C formatting only.

4.3

SMBus Protocols

The CAP1133 is SMBus 2.0 compatible and supports Write Byte, Read Byte, Send Byte, and Receive Byte as valid

protocols as shown below.

All of the below protocols use the convention in Table 4-1.

4.3.1

SMBUS WRITE BYTE

The Write Byte is used to write one byte of data to a specific register as shown in Table 4-2.

4.3.2

SMBUS READ BYTE

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4-3.

TABLE 4-1:

PROTOCOL FORMAT

Data Sent to

Device

Data Sent to the

HOst

Data sent

TABLE 4-2:

WRITE BYTE PROTOCOL

Start

Slave

Address

ACK

Address

ACK

Stop

1 ->0

0101_000

XXh

0 -> 1

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