LAN8820I datasheet(70/83 Pages) MICROCHIP

70 / 83 page

LAN8820/LAN8820I

DS00001871B-page 70

 2009-2015 Microchip Technology Inc.

5.5.5.2

PHY TXC Delay Disabled Timing

Note 5-6

7.2ns for 1000BASE-T operation, 36ns for 100BASE-TX operation, 360ns for 10BASE-T operation.

Minimum limits are non-sustainable long term.

Note 5-7

8ns for 1000BASE-T operation, 40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.

Note 5-8

8.8ns for 1000BASE-T operation, 44ns for 100BASE-TX operation, 440ns for 10BASE-T operation.

Maximum limits are non-sustainable long term.

Note 5-9

45% for 1000BASE-T operation, 40% for 100BASE-TX or 10BASE-T operation.

Note 5-10

55% for 1000BASE-T operation, 60% for 100BASE-TX or 10BASE-T operation.

FIGURE 5-6:

RGMII PHY TXC DELAY DISABLED TIMING

TABLE 5-15:

RGMII PHY TXC DELAY DISABLED TIMING VALUES

Symbol

Description

Min

Typ

Max

Units

ttxc

TXC period

Note 5-6

Note 5-7

Note 5-8

tclkh

TXC high time

Note 5-9

Note 5-10

tclkl

TXC low time

Note 5-9

Note 5-10

tsetup

TXD[3:0], TXCTRL setup time to edge of TXC

1.0

thold

TXD[3:0], TXCTRL hold time after edge of TXC

0.8

TXC

TXD[3:0]

TXCTRL

tclkh

tclkl

ttxc

thold

tsetup

TXD

[3:0]

TXD

[7:4]

TXEN

TXER

thold

tsetup

thold

tsetup

thold

tsetup

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