LAN8820I datasheet(18/83 Pages) MICROCHIP

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LAN8820/LAN8820I

DS00001871B-page 18

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3.3

RGMII Interface

The device communicates with an external MAC using the Reduced Gigabit Media Independent Interface (RGMII). The

RGMII is compliant with the RGMII standard, and provides support for 1000BASE-T, 100BASE-TX, or 10BASE-T oper-

ation.

The RGMII consists of the RXC, RXD[3:0], RXCTRL, TXC, TXD[3:0] and TXCTRL signals. All transmission related sig-

nals, TXC, TXD[3:0] and TXCTRL, are generated by the MAC. The TXC transmit clock is used to synchronize the

TXD[3:0] data and TXCTRL control signals. All reception related signals, RXC, RXD[3:0] and RXCTRL, are generated

by the device. The RXC receive clock is used to synchronic the RXD[3:0] data and RXCTRL control signals.

The RGMII interface supports both Version 1.3 and Version 2.0 of the RGMII specification. Version 1.3 of the RGMII

Specification requires a 1.5 to 2ns clock delay via a PCB trace delay. Version 2.0 of the RGMII Specification introduces

the option of an on-chip Internal Delay (ID). These distinct RGMII modes of operation are referred to as “Non-ID Mode”

and “ID Mode”, respectively, throughout the document. Refer to the RGMII specification for additional details.

In addition to the standard Non-ID and ID modes of operation, the device supports a hybrid mode of operation, for a

total of 3 RGMII modes. These modes are summarized below:

Non-ID Mode

- Per the RGMII specification, no internal delay is generated at the MAC or the device(PHY). External

PCB trace delays are required to meet RGMII timing requirements.

ID Mode

- Per the RGMII specification, an internal delay is generated on TXC at the MAC, and an ID is generated on

RXC at the device(PHY). No PCB trace delay is required.

Hybrid Mode

- In this mode, the device(PHY) will generate an ID on both TXC and RXC. This mode may be used to

eliminate the PCB trace delay requirement when utilizing a non-ID MAC.

The RGMII mode is configured via the RGMII PHY TXC Delay Enable and RGMII PHY RXC Delay Enable bits of the

Control / Status Indications Register (29.[9:8]). The default values of these bits are configured via the RGMII_ID_MODE

configuration strap. Figure 3-2 details the RGMII mode configuration logic. For additional information on the RGMII_ID_-

MODE configuration strap, refer to Section 3.8.1.1, "Configuration Straps," on page 24.

FIGURE 3-2:

RGMII MODE CONFIGURATION LOGIC

PHY TX Logic

TXC

(From MAC)

Delay

TXD[3:0]

(From MAC)

LAN8820/LAN8820i

RXC

(To MAC)

Delay

RXD[3:0]

(To MAC)

PHY RX Logic

RGMII PHY TXC

Delay Enable Bit

RGMII_ID_MODE

RGMII PHY RXC

Delay Enable Bit

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