MEC1322 datasheet(51/456 Pages) MICROCHIP

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DS00001719D-page 51

MEC1322

Note 3-5

The chipset will not produce a valid 32KHz clock until about 5 ms (PCH) or 110 ms (ICH) after the

deassertion of RSMRST#. See chipset specification for the actual timing.

Note 3-6

The 48 MHz Ring Oscillator is reset by VCC1GD.

Note 3-7

The Clock Enable Register contains the XOSEL bit and the 32K_EN bit (see Section 4.7.2, "Clock

Enable Register," on page 73). The 32.768 KHz Oscillator provides a stable timebase for the 48 MHz

Ring Oscillator as well as the clock source for the 32KHz Clock Domain. After VBAT POR there is a

500ms max time for the 48 MHz Ring Oscillator to become accurate.

3.5.1

32KHZ CLOCK SWITCHING

The 32kHz clock switching logic switches the clock source of the 32kHz clock domain to be either the single-ended

32.768 KHz clock input or the 32.768 kHz Crystal Oscillator. If neither of these is available, this clock domain is derived

from the 48 MHz Ring Oscillator.

Following a VBAT_POR, the XOSEL bit and the 32K_EN bit in the Clock Enable Register are programmed to configure

the source of this clock domain.

If the single-ended 32.768 KHz clock input is configured as the source of the 32kHz clock domain, then following a

VCC1_RESET, the time for this clock domain to become accurate at 32.768kHz after the SUSCLK input goes active is

100us (max).

If the 32.768 kHz Crystal Oscillator is configured as the source of the 32kHz clock domain, then following a VCC1_RE-

SET, there is 100us (max) delay time for this clock domain to become accurate at 32.768kHz.

3.5.2

CLOCK DOMAINS VS. ACPI POWER STATES

Table 3-6, "Typical MEC1322 Clocks vs. ACPI Power States" shows the relationship between ACPI power states and

MEC1322 clock domains:

TABLE 3-6:

TYPICAL MEC1322 CLOCKS VS. ACPI POWER STATES

Clock

Name

ACPI Power State

Description

(FULL

ON)

(POS)

(STR)

(STD)

(Soft

Off)

(MECH

Off)

SUSCLK

OFF

This clock is the system

suspend clock source.

(Note 3-5).

32.768 kHz Crystal

Oscillator

This clock is generated

from a 32.768 KHz paral-

lel resonant crystal con-

nected between the

XTAL1 and XTAL2 pins.

32KHz_Clk

ON/ OFF This clock domain is gen-

erated from the 32KHz

clock input (SUSCLK)

when available or the

crystal oscillator pins.

Otherwise it is generated

internally from the 48

MHz Ring Oscillator.

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