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MEC1322 Datasheet(PDF) 76 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 76 Page - Microchip Technology |
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76 / 456 page ![]() MEC1322 DS00001719D-page 76 2014 - 2015 Microchip Technology Inc. 5.4 Interface This block is designed to be accessed externally via the pin interface and internally via a registered host interface. 5.4.1 SIGNAL DESCRIPTION FIGURE 5-1: BLOCK DIAGRAM OF LPC INTERFACE CONTROLLER WITH CLKRUN# SUPPORT TABLE 5-2: SIGNAL DESCRIPTION TABLE Name Direction Description LAD0 Input/Output Bit[0] of the LPC multiplexed command, address, and data bus. LAD1 Input/Output Bit[1] of the LPC multiplexed command, address, and data bus. LAD2 Input/Output Bit[2] of the LPC multiplexed command, address, and data bus. LAD3 Input/Output Bit[3] of the LPC multiplexed command, address, and data bus. SERIRQ LAD0 LAD1 LAD2 LAD3 LFRAME# LRESET# LCLK LPC Interface (Logical Device Ch) LPC Controller Serial IRQ State Machine Interface to Configuration Registers CLKRUN# LPC Config Registers LPC Regis- ters (Runtime, EC-Only) Interface to Logical Device Register |
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