ADS5294IPFPR datasheet(36/81 Pages) TI1

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ADS5294

SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015

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NOTE

For certain sampling frequencies, there are two PLL states possible, both of which are

stable. In such cases, the higher PLL state results in a better set-up time compared to a

lower PLL state. For example, at 80 MSPS, with decimation by 2 enabled, the PLL may be

in states 3 or 4. However, the set-up time value specified in LVDS Timing at Different

Sampling Frequencies — 1-Wire Interface, 14x-Serialization, Decimation by 2 Filter

Enabled (0.43 ns minimum) is in PLL state 4. In state 3, the set-up time is reduced further

by 100 ps typically, with a corresponding increase in the hold time.

Table 2. PLL Configuration When Decimation is Disabled

ADC Fs (MSPS)

FUNCTION

≤ 12

Disable PLL auto state switch and put

0xD1

0x0040

PLL in state 1

≤ Fs ≤ 24

Disable PLL auto state switch and put

0xD1

0x00C0

PLL in state 2

≤ Fs ≤ 42

Disable PLL auto state switch and put

0xD1

0x0140

PLL in state 3

≥ 28

Disable PLL auto state switch and put

0xD1

0x0240

PLL in state 4

Table 3. PLL Configuration When Decimation by 2 is Used

ADC Fs

FUNCTION

≤ 24

Disable PLL auto state switch and put

0xD1

0x0040

PLL in state 1

≤ Fs ≤ 48

Disable PLL auto state switch and put

0xD1

0x00C0

PLL in state 2

≤ Fs ≤ 80

Disable PLL auto state switch and put

0xD1

0x0140

PLL in state 3

≥ 56

Disable PLL auto state switch and put

0xD1

0x0240

PLL in state 4

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