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ADS5294IPFPR Datasheet(PDF) 1 Page - Texas Instruments |
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ADS5294IPFPR Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 81 page  CLOCKGEN PLL LCLKP LCLKN ACLKP ACLKN REFERENCE CONTROL INTERFACE CLKP CLKN ADS5294 14 bit ADAC 14 BIT ADC DIGITAL PROCESSING BLOCK SAMPLING CIRCUIT SERIALIZER INxP INxN OUTxA_P OUTxA_N OUTxB_P OUTxB_N SYNC 1 of 8 Channels Product Folder Sample & Buy Technical Documents Tools & Software Support & Community ADS5294 SLAS776D – NOVEMBER 2011 – REVISED SEPTEMBER 2015 ADS5294 Octal-Channel 14-Bit 80-MSPS High-SNR and Low-Power ADC 1 Features 3 Description The ADS5294 is a low-power 80-MSPS 8-Channel 1 • Maximum Sample Rate: 80 MSPS/14-Bit ADC that uses CMOS process technology and • High Signal-to-Noise Ratio innovative circuit techniques. Low power – 75.5-dBFS SNR at 5 MHz / 80 MSPS consumption, high SNR, low SFDR, and consistent overload recovery allow users to design high- – 78.2-dBFS SNR at 5 MHz / 80 MSPS and performance systems. Decimation Filter Enabled The digital processing block of the ADS5294 – 84-dBc SFDR at 5 MHz / 80 MSPS integrates several commonly used digital functions for • Low Power Consumption improving system performance. The device includes – 58 mW/CH at 50 MSPS a digital filter module that has built-in decimation – 77 mW/CH at 80 MSPS (2-LVDS Wire Per filters (with lowpass, highpass and bandpass characteristics). The decimation rate is also Channel) programmable (by 2, by 4, or by 8). This rate is useful • Digital Processing Block for narrow-band applications, where the filters are – Programmable FIR Decimation Filter and used to conveniently improve SNR and knock-off Oversampling to Minimize Harmonic harmonics, while at the same time reducing the Interference output data rate. The device includes an averaging mode where two channels (or even four channels) – Programmable IIR High-Pass Filter to Minimize are averaged to improve SNR. DC Offset – Programmable Digital Gain: 0 dB to 12 dB Device Information(1) – 2-Channel or 4-Channel Averaging PART NUMBER PACKAGE BODY SIZE (NOM) • Flexible Serialized LVDS Outputs: ADS5294 HTQFP (80) 12.00 mm × 12.00 mm – One or Two Wires of LVDS Output Lines Per (1) For all available packages, see the orderable addendum at Channel Depending on ADC Sampling Rate the end of the data sheet. – Programmable Mapping Between ADC Input Simplified Block Diagram Channels and LVDS Output Pins-Eases Board Design – Variety of Test Patterns to Verify Data Capture by FPGA/Receiver • Internal and External References • 1.8-V Operation for Low Power Consumption • Low-Frequency Noise Suppression • Recovery From 6-dB Overload Within 1 Clock Cycle • Package: 12-mm × 12-mm 80-Pin QFP 2 Applications • Ultrasound and Sonar Imaging • Communication Applications • Multi-channel Data Acquisition 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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