C164CI datasheet(39/53 Pages) INFINEON

39 / 53 page

Semiconductor Group

1998-02

C164CI

Phase Locked Loop

For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is

enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by

the factor F which is selected via the combination of pins P0.15-13 (ie. fCPU = fXTAL * F). With every

F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This

synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly.

Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked

to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs.

The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the

minimum TCL that is possible under the respective circumstances.

The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly

adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)

the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula

and figure below).

For a period of

N * TCL the minimum value is computed using the corresponding deviation DN:

TCLmin = TCLNOM * (1 - DN / 100)

DN = ±(4 - N /15) [%],

where

N = number of consecutive TCLs

and 1

≤ N ≤ 40.

So for a period of 3 TCLs (ie.

N = 3): D3 = 4 - 3/15 = 3.8%,

and (3TCL)min = 3TCLNOM * (1 - 3.8 / 100) = 3TCLNOM * 0.962 (57.72 nsec @ fCPU = 25 MHz).

This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial

interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or

measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.

Figure 10

Approximated Maximum PLL Jitter

±1

±2

±3

±4

Max.jitter [%]

This approximated formula is valid for

≤ N ≤ 40 and 10MHz ≤ f

CPU ≤ 25MHz.

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