VX6953CB datasheet(26/107 Pages) STMICROELECTRONICS

26 / 107 page

Functional description

VX6953CB

26/107

8209023 Rev 5

3.4.4

Failsafe signals

All signals going into the VX6953CB must be at either a low state or a high impedance when

power is removed from the device. The exceptions to this rule are the EXTCLK,

XSHUTDOWN and the CCI signals. These pads have been designed to be high impedance

when the VX6953CB is powered-down. This means that the input signal on the specified

pads can either be high or low with no leakage problems.

3.5

Clock and frame rate timing

3.5.1

Video frame rate control

The output frame rate of VX6953CB can be reduced by extending either the line length or

the frame length. The extension is achieved by adding extra blanking bytes at the end of a

line or ‘blank’ video lines to act as timing padding. The frame rate can be reduced from the

default 15 frame/s at 5.0 Mpixel resolution to less than 3 frame/s at 5.0 Mpixel resolution.

The advantage of the frame extension approach is that it does not reduce the pixel readout

rate or the active frame time and therefore does not introduce unwanted motion distortion

effects to the image.

3.5.2

PLL and clock input

The VX6953CB has an embedded PLL block. This block generates all necessary internal

clocks from an input range defined in Table 8. The input clock pad accepts up to 27 MHz

signals. The input clock can be a sine wave or square wave.

Table 8. System input clock frequency range

Min. (MHz)

Max. (MHz)

VX6953CB Datasheet(PDF) 26 Page - STMicroelectronics