TLE6244 datasheet(30/70 Pages) INFINEON

30 / 70 page

Final Data Sheet

V4.2, 2003-08-29

TLE 6244X

1.7 µsec - Bus Interface

The µsec-bus-interface is one of three possibilities to control the power stages. OUT1...OUT7

and OUT9...OUT16 are influenced by the reset input RST. If RST is set to Low, these power

stages are switched off. After reset they are controlled by the SPI (default initialization of

TLE6244X). Power stage 8 however is not influenced by the reset input if it’s controlled by IN8

and UVDD > 3,5V. Alternatively these outputs can be controlled either by the pins IN1...IN16 or by

the µsec-bus interface. Exception: OUT8 can be controlled by IN8 or by the SPI-interface only.

The bit ’Bus-Multiplex’ (BMUX) in the SPI register CONFIG prescribes parallel access (IN1...IN7,

IN9...IN16) or µsec-bus control (see figure below). Exception: If BMUX is set to ‘0’ only the power-

stages OUT1...OUT7 and OUT9...OUT16 are controlled by the µsec-bus.

Main features:

- 16 data bits for each data-frame (at the pin FDA)

- 16 clock-pulses for each data-frame (at the pin FCL)

- clock frequency TLE6244: 0...16 MHz

- one sync -input (pin SSY) to latch the input data stream

- input level interface same as for IN6, IN7, IN16

- no error correction

SSY

FCL

don’t care

D15

D14

Data-Frame

FDA

16 bit shift register

FDA

FCL

SSY

SCON_REG

Principle of the µsec-bus interface

16 bit µsec-bus Reg.

SPI-shift-reg

SPI

INx

BMUX

MUX_REG

OUTx

Glitch

Filter

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