ATMEGA8 datasheet(67/303 Pages) ATMEL

67 / 303 page

ATmega8(L)

2486M–AVR–12/03

8-bit Timer/Counter0

Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The

main features are:

• Single Channel Counter

• Frequency Generator

• External Event Counter

• 10-bit Clock Prescaler

Overview

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For the

actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible

I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O

page 70.

Figure 26. 8-bit Timer/Counter Block Diagram

Registers

The Timer/Counter (TCNT0) is an 8-bit register. Interrupt request (abbreviated to

Int. Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).

TIFR and TIMSK are not shown in the figure since these registers are shared by other

timer units.

The Timer/Counter can be clocked internally or via the prescaler, or by an external clock

source on the T0 pin. The Clock Select logic block controls which clock source and edge

the Timer/Counter uses to increment its value. The Timer/Counter is inactive when no

clock source is selected. The output from the clock select logic is referred to as the timer

clock (clk

T0).

Definitions

Many register and bit references in this document are written in general form. A lower

case “n” replaces the Timer/Counter number, in this case 0. However, when using the

accessing Timer/Counter0 counter value and so on.

The definitions in Table 33 are also used extensively throughout this datasheet.

Timer/Counter

TCNTn

Control Logic

= 0xFF

count

TOVn

(Int.Req.)

TCCRn

Clock Select

Edge

Detector

( From Prescaler )

clk

Table 33. Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes 0x00

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

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