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ADC0820CCWM Datasheet(PDF) 12 Page - National Semiconductor (TI) |
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ADC0820CCWM Datasheet(HTML) 12 Page - National Semiconductor (TI) |
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12 / 22 page ![]() 1.0 Functional Description (Continued) OTHER INTERFACE CONSIDERATIONS In order to maintain conversion accuracy, WR has a maxi- mum width spec of 50 µs. When the MS flash ADC’s sampled-data comparators (Section 1.2) are in comparison mode (WR is low), the input capacitors (C, Figure 8 ) must hold their charge. Switch leakage and inverter bias current can cause errors if the comparator is left in this phase for too long. Since the MS flash ADC enters its zeroing phase at the end of a conversion (Section 1.3), a new conversion cannot be started until this phase is complete. The minimum spec for this time (t P, Figures 2, 3, 4, 5 ) is 500 ns. DS005501-20 Note: MS means most significant LS means least significant FIGURE 11. Operating Sequence (WR-RD Mode) www.national.com 12 |
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