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PI6LC4833 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation |
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PI6LC4833 Datasheet(HTML) 1 Page - Pericom Semiconductor Corporation |
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1 / 13 page ![]() 1 www.pericom.com P-0.1 06/14/11 Alltrademarksarepropertyoftheirrespectiveowners. PI6LC4833 Pin Configuration (56-Pin TQFN) OC-A FA0 FA1 SS1 PLL_BYPS VSEL_33 VCCC1 QC1 VCCC0 QC0- QC0+ SEL_FREQ3 QC-C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 SS0 GND FB1 FB0 OC-B VCCB QB1 VDD_OSC X1 X2 IN+ IN- IN_Sel OC-R Sel_Freq2 QB0 Description The PI6LC4833 implements Pericom's advanced LC VCO tech- nology and is specifically designed for Power PC network pro- cessor (Freescale MPC8548, MPC8572, AMCC 460, AMI732). This high performance device is optimized to generate CPU core/ PCI clock, high performance PCIe Gen1/2 Clock, SRIO, Gigabit Ethernet’s MAC and PHY clock. All outputs are generated from 25MHz external clock input or crystal. Application Î Î Router/Switch Î Î OLT, BSC, WLAN, Wireless gateway Î Î Wireless Features Î Î 2.5/3.3V supply voltage Î Î 4 HCSL 100/125/200/250MHz outputs with OE Î Î 2 LVCMOS 33/50/66/100MHz selectable outputs Î Î 5 LVCMOS 25MHz or 125MHz outputs Î Î 1 LVPECL 312.5MHz, 156.25MHz or 125MHz output Î Î 1 CMOS 156.25MHz or 125MHz output Î Î 1 LVPECL 125MHz or 25MHz output Î Î 25MHz crystal or differential input Î Î 0.5ps (typ) RMS integrated phase noise design at 3.3V operation Î Î 1.0ps (typ) RMS integrated phase noise design at 2.5V operation Î Î PLL Bypass mode for test Î Î Industrial Temperature -40°C to 85°C Î Î TQFN - 56 package Clock Generator for Power PC 11-0074 |
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