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MB9AF112LA Datasheet(PDF) 56 Page - SPANSION |
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MB9AF112LA Datasheet(HTML) 56 Page - SPANSION |
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56 / 121 page  D a t a S h e e t December 16, 2014, MB9A110A-DS706-00011-3v0-E 53 CONFIDENTIAL BLOCK DIAGRAM Flash I/F Cortex-M3 Core @40 MHz(Max) Clock Reset Generator Dual-Timer WatchDog Timer (Hardware) DMAC 8ch Multi-Function Timer x 2 Multi-Function Serial I/F 8ch. (with FIFO ch.4 to 7) & HW flow control(ch.4) * 2 16-bit Free-Run Timer 3ch. 16-bit Output Compare 6ch. 16-bit Input Capture 4ch. Waveform Generator 3ch. A/D Activation Compare 3ch. 16-bit PPG 3ch. Watch Counter Unit 0 GPIO CSV LVD External Interrupt Controller 16-pin + NMI Power-On Reset TPIU* 1 ROM Table ETM* 1 SRAM0 8/16 Kbyte SWJ-DP SRAM1 8/16 Kbyte I D Sys MB9AF111LA/MA/NA, F112LA/MA/NA, F114LA/MA/NA, F115MA/NA, F116MA/NA Base Timer 16-bit 8ch. / 32-bit 4ch. NVIC WatchDog Timer (Software) Security 12-bit A/D Converter x 3 Unit 1 Unit 2* 2 TRSTX,TCK, TDI,TMS TRACED[3:0], TRACECLK AN[15:0] TIOA[7:0] TIOB[7:0] IC0[3:0] DTTI[1:0]X RTO0[5:0] FRCK[1:0] C TDO SCK[7:0] SIN[7:0] SOT[7:0] INT[15:0] NMIX P0[F:0], P1[F:0], . . . Px[x:0] INITX MODE-Ctrl IRQ-Monitor PIN-Function-Ctrl MD[1:0] Regulator QPRC 2ch. AIN[1:0] BIN[1:0] ZIN[1:0] LVD Ctrl CRC Accelerator IC1[3:0] ADTGx RTS4 CTS4 External Bus I/F* 2 MAD[24:0] MADATA[15:0] MCSX[7:0], MOEX,MWEX, MALE, MRDY, MCLKOUT, MDQM[1:0] RTO1[5:0] On-Chip Flash 64/128/256/384/512 Kbyte X0 X1 X0A PLL CLK CR 100kHz Source Clock CROUT Main Osc Sub Osc CR 4MHz AVCC, AVSS,AVRH *1: For the MB9AF111LA/MA, F112LA/MA, MB9AF114LA/MA, MB9AF115MA and MB9AF116MA, ETM is not available. *2: For the MB9AF111LA, F112LA and MB9AF114LA, the External Bus Interface and 12-bit A/D Converter (unit 2) are not available. And the Multi-function Serial Interface does not support hardware flow control in these products. |
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