MB9AF112LA datasheet(6/121 Pages) SPANSION

6 / 121 page

D a t a S h e e t

December 16, 2014, MB9A110A-DS706-00011-3v0-E

CONFIDENTIAL

 External Bus Interface*

 Supports SRAM, NOR Flash device

 Up to 8 chip selects

 8/16-bit Data width

 Up to 25-bit Address bit

 Maximum area size : Up to 256 Mbytes

 Supports Address/Data multiplex

 Supports external RDY function

* : MB9AF111LA, F312LA and F314LA do not support External Bus Interface

 DMA Controller (8channels)

The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process

simultaneously.

 8 independently configured and operated channels

 Transfer can be started by software or request from the built-in peripherals

 Transfer address area: 32bit(4Gbytes)

 Transfer mode: Block transfer/Burst transfer/Demand transfer

 Transfer data type: byte/half-word/word

 Transfer block count: 1 to 16

 Number of transfers: 1 to 65536

 A/D Converter (Max 16channels)

[12-bit A/D Converter]

 Successive Approximation type

 Built-in 3units*

 Conversion time: 1.0μs@5V

 Priority conversion available (priority at 2levels)

 Scanning conversion mode

 Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:

4steps)

* : MB9AF111LA, F112LA , F114LA built-in 2units

 Base Timer (Max 8channels)

Operation mode is selectable from the followings for each channel.

 16-bit PWM timer

 16-bit PPG timer

 16/32-bit reload timer

 16/32-bit PWC timer

MB9AF112LA Datasheet(PDF) 6 Page - SPANSION