PI7VD9004ABH datasheet(11/73 Pages) PERICOM

11 / 73 page

PI7VD9008ABH

Adaptive EQ 8-channel 960H Video Decoder

www.pericom.com

12/12/14

PIXCLK_P

VIN_0

VIN_1

PIXCLK_N

Cb0

Cb10

Y10

Cr10

Y11

Cb11

Y11

PIXOUT_x

Cb10

Y10

Cr10

Y11

Cb0

Cb11

Y11

Time-multipexed Format with 54/ 72MHz

ANALOG AUDIO INPUT

The audioADC offers 5 channels of analog inputs (LINE_INx, x= 0, 1, 2, 3, 4, 5, 6, 7, 8, 9) with a peak-to-peak voltage range from

0.5V to 2V. Each input channel contains 4-bit programmable gain amplifier and an ADC with maximum over-sampling speed of 3.6M

Sample/s. A pseudo differential input is used to minimize board level noise problems. The converted audio data stream is fed into a low

pass filter to decimate audio sample at an appropriate audio sampling rate such as 8 KHz, 16 KHz, 32 KHz, 44.1 KHz and 48 KHz etc.

AUDIO PROCESSING

The audio processor accepts 5 digital audio streams from audio ADC. It also receives 2 additional digital serial audio data from pins.

One digital serial audio data is SDIN_P coming from AV compression processor, while the other one is SD_LINKI coming from com-

panion device.

SDIN_P represents the decompressed audio data for playback purpose. SD_LINKI is used to cascade with digital audio outputs from

one other PI7VD9008ABH chips for forming one timing multiplexed I2S digital serial audio data containing 8 or 10 digital audio

channels. This device processes these 10 digital audio streams and 2 digital serial audio data, then generates one mixing analog audio

signal and three digital serial audio data to fulfill the functions of mixing, recording and cascading etc.

For audio mixing, this device has both analog and digital format. The built-in mixer selects among all audio input data to generate the

mixing digital audio data (SDOUT_M), which connects to audio DAC for converting to mixing analog audio signal output (LINE_OUT).

For audio recording, the audio processor performs multiplexing over 16 digital audio streams in timing division way to generate record

digital audio output data (SDOUT_R). For the digital serial audio data SDOUT_R and SDOUT_M, they are both synchronized with

SCLK_R and LRCK_R. As to SDIN_P, it is synchronized with SCLK_P and LRCK_P. These digital serial audio data support two

formats of I2S and DSP that can be selected by control bits RM_SYNC in the register at offset 0xD2 and PB_SYNC in the register at

offset 0xDB. Meanwhile, the record and playback digital serial audio interfaces of PI7VD9008ABH can be acted as Master or Slave

mode based upon the setting of ACLKRMASTER and PB_MASTER bits in the register at offset 0xDB

This device supports audio system clock with 256fs or 320fs mode, which is controlled by AIN5MD register. The record output pin con-

tains several channel inputs that can be defined by the registers at offset of 0xD2~ 0xDAdescribing the number and sequence of recorded

audio streams. It supports 8bit and 16bit record data width for trading off between higher audio qualities and saving disk storage space.

By controlling bit2 of register at offset 0xDB, the chip allows to select the output record data width to be either 8-bit or 16-bit mode.

14-0207

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