TAS3103DBT datasheet(57/146 Pages) TI

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2−25

GPIO0

GPIO1

GPIO2

GPIO3

Sample

Logic

0xEF

Down

Counter

LRCLK

Decode 0

DATA PATH SWITCH

GPIODIR

Determines How Many Consecutive Logic 0 Samples

(Where Each Sample Is Spaced by GPIOFSCOUNT

LRCLKs) are Required to Read a Logic 0 on a

GPIO Input Port

S Slave Addr

Sub-Addr

Ack

00000000

Ack

21 0

0000

Ack GPIOFSCOUNT Ack GPIO_samp_int Ack

23 20 19

Microprocessor

Firmware

Microprocessor

Control

0xEE

GPIO_in_out

S Slave Addr

Sub-Addr

Ack

00000000

Ack

21 0

Ack

00000000

00000000 Ack

0000

Ack

I2C Slave Mode

and

I2C Master Mode

Write

I2C Master

Mode Read

Figure 2−21. GPIO Port Circuitry

2.8.1

GPIO Functionality—I2C Master Mode

In the I2C master mode, the GPIO ports are strictly input ports and are used to control volume. Table 2−6 lists the

functionality of each GPIO port in the I2C master mode. Bit field GPIOFSCOUNT (15:8) of I2C subaddress 0xEF

governs the rate at which the GPIO pins are sampled for a volume update. The sample rate is:

GPIO_Port +

LRCLK

GPIOFSCOUNT

Table 2−6. GPIO Port Functionality—I2C Master Mode

GPIO PORT

FUNCTION

GPIO0 (pin 18)

Volume up—CH1 and CH2

GPIO1 (pin 19)

Volume down—CH1 and CH2

GPIO2 (pin 20)

Volume up—CH3

GPIO3 (pin 21)

Volume down—CH3

GPIOFSCOUNT also governs the rate at which the power down pin PWRDN is sampled and the rate at which the

watchdog counter is reset. GPIOFSCOUNT then cannot be independently used to tune the volume adjustment. For

this reason, bit field GPIO_samp_int of the same I2C subaddress (0xEF) is included to provide the ability to adjust

the responsiveness (or sluggishness) of the volume switches.

Each GPIO port has a weak pullup to VDDS. A volume control switch then typically switches the signal line to the GPIO

port between ground and an open circuit. The parameter GPIO_samp_int sets how many consecutive GPIO port

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