DS1921 datasheet(37/44 Pages) DALLAS

37 / 44 page

DS1921H/Z

37 of 44

STEP 2

Set the EMCLR bit to 1, enable the RTC and then execute the Clear Memory command. The RTC

oscillator must be stable before the Clear Memory command is issued. Wait 500 µs after issuing the Clear

Memory command before proceeding to Step 3. This results in the following data to be written to the

Status Register:

Address:

20Eh

Data:

40h

With only a single DS1921H/Z connected to the bus master, the communication of step 2 is as follows:

MASTER MODE

DATA (LSB FIRST)

COMMENTS

(Reset)

Reset pulse (480µs to 960µs)

(Presence)

Presence pulse

CCh

Issue Skip ROM command

0Fh

Issue Write Scratchpad command

0Eh

TA1, beginning offset = 0Eh

02h

TA2, address = 020Eh

40h

Write status byte to scratchpad

(Reset)

Reset pulse

(Presence)

Presence pulse

CCh

Issue Skip ROM command

AAh

Issue Read Scratchpad command

0Eh

Read TA1, beginning offset = 0Eh

02h

Read TA2, address = 020Eh

0Eh

Read E/S, ending offset = 0Eh, flags = 0h

40h

Read scratchpad data and verify

(Reset)

Reset pulse

(Presence)

Presence pulse

CCh

Issue Skip ROM command

55h

Issue Copy Scratchpad command

0Eh

02h

0Eh

TA1

TA2

(AUTHORIZATION CODE)

E/S

(Reset)

Reset pulse

(Presence)

Presence pulse

CCh

Issue Skip ROM command

3Ch

Issue Clear Memory command

(Reset)

Reset pulse

(Presence)

Presence pulse

DS1921 Datasheet(PDF) 37 Page - Dallas Semiconductor

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