COP888EB datasheet(36/75 Pages) NSC

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Frame Formats (Continued)

SYNCHRONIZATION

Every receiver starts with a “hard synchronization” on the

falling edge of the SOF bit. One bit time consists of four bit

segments: Synchronization segment, propagation segment,

phase segment 1 and phase segment 2.

A falling edge of the data signal should be in the synchroni-

zation segment. This segment has the fixed length of one

time quanta. To compensate for the various delays within a

network, the propagation segment is used. Its length is pro-

grammable from 1 to 8 time quanta. Phase segment 1 and

phase segment 2 are used to resynchronize during an active

frame. The length of these segments is from 1 to 8 time

quanta long.

Two types of synchronization are supported:

Hard synchronization is done with the falling edge on the

bus while the bus is idle, which is then interpreted as the

SOF. It restarts the internal logic.

Soft synchronization is used to lengthen or shorten the bit

time while a data or remote frame is received. Whenever a

falling edge is detected in the propagation segment or in

phase segment 1, the segment is lengthened by a specific

value, the resynchronization jump width (see

Figure 29 ).

If a falling edge lies in the phase segment 2 (as shown in

Fig-

ure 29 ) it is shortened by the resynchronization jump width.

Only one resynchronization is allowed during one bit time.

The sample point lies between the two phase segments and

is the point where the received data is supposed to be valid.

The transmission point lies at the end of phase segment 2 to

start a new bit time with the synchronization segment.

The resynchronization jump width (RJW) is automati-

cally determined from the programmed value of PS. If a

soft resynchronization is done during phase segment 1

or the propagation segment, then RJW will either be

equal to 4 internal CAN clocks (CKI/(1

+ divider))orthe

programmed value of PS, whichever is less. PS2 will

never be shorter than 1 internal CAN clock.

(PS1 — BTL settings any PSC setting) The PS1 of the

BTL should always be programmed to values greater

than 1. To allow device resynchronization for positive

and negative phase errors on the bus. (if PS1 is pro-

grammed to one, a bit time could only be lengthened

and never shortened which basically disables half of the

synchronization).

DS012837-32

FIGURE 27. CAN Bus States

DS012837-33

A) Synchronization segment

B) Propagation segment

FIGURE 28. Bit Timing

COP888EB Datasheet(PDF) 36 Page - National Semiconductor (TI)

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