COP888EB datasheet(65/75 Pages) NSC

65 / 75 page

Memory Map (Continued)

Address

Contents

00CB

A/D Converter Control

00CC

A/D Converter Result Register

(Reg:ADRSLT)

00CD to

00CE

Reserved

00CF

IDLE Timer Control Register

(Reg:ITMR)

00D0

PORTLD, Port L Data

00D1

PORTLC, Port L

Configuration Register

00D2

PORTLP, Port L Input Pins

(Read Only)

00D3

Reserved for Port L

00D4

PORTGD, Port G Data

00D5

PORTGC, Port G

Configuration Register

00D6

PORTGP, Port G Input Pins

(Read Only)

00D7

Port I Input Pins (Read Only)

00D8

Port CD, Port C Data Register

00D9

Port CC, Port C Configuration

00DA

Port CP, Port C Input Pins

(Read Only)

00DB

Reserved for Port C

00DC

Port D

00DD to

00DF

Reserved for Port D

00E0 to

00E5

Reserved for EE Control

Registers

00E6

Timer T1 Autoload Register

T1RB Lower Byte (T1BRLO)

00E7

Timer T1 Autoload Register

T1RB Upper Byte (T1BRHI)

00E8

ICNTRL Register

00E9

MICROWIRE/PLUS Shift

00EA

Timer T1 Lower Byte

(TMR1LO)

00EB

Timer T1 Upper Byte

(TMR1HI)

00EC

Timer T1 Autoload Register

T1RA Lower Byte (T1RALO)

00ED

Timer T1 Autoload Register

T1RA Upper Byte (T1RAHI)

00EE

CNTRL, Control Register

00EF

PSW, Processor Status Word

Address

Contents

00F0 to

00FB

On-Chip RAM Mapped as

Registers

00FC

X Register

00FD

SP Register

00FE

B Register

00FF

S Register

0100 to 013F

On-Chip RAM Bytes (64

Bytes)

Reading memory locations 0070H–007FH will

return all ones.

Reading unused memory locations 00xxH–00xxH

will return undefined data.

Addressing Modes

There are ten addressing modes, six for operand addressing

and four for transfer of control.

OPERAND ADDRESSING MODES

This is the “normal” addressing mode. The operand is the

data memory addressed by the B pointer or X pointer.

decrement of pointer)

This addressing mode is used with the LD and X instruc-

tions. The operand is the data memory addressed by the B

pointer or X pointer. This is a register indirect mode that au-

tomatically post increments or decrements the B or X regis-

ter after executing the instruction.

Direct

The instruction contains an 8-bit address field that directly

points to the data memory for the operand.

Immediate

The instruction contains an 8-bit immediate field as the oper-

and.

Short Immediate

This addressing mode is used with the Load B Immediate in-

struction. The instruction contains a 4-bit immediate field as

the operand.

Indirect

This addressing mode is used with the LAID instruction. The

contents of the accumulator are used as a partial address

(lower 8 bits of PC) for accessing a data operand from the

program memory.

TRANSFER OF CONTROL ADDRESSING MODES

Relative

This mode is used for the JP instruction, with the instruction

field being added to the program counter to get the new pro-

gram location. JP has a range from −31 to +32 to allow a

1-byte relatie jump (JP + 1 is implemented by a NOP instruc-

tion). There are no “pages” when using JP, since all 15 bits of

PC are used.

COP888EB Datasheet(PDF) 65 Page - National Semiconductor (TI)

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