| Electronic Components Datasheet Search |
|
M68SDIL Datasheet(PDF) 51 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
M68SDIL Datasheet(HTML) 51 Page - Motorola, Inc |
|
51 / 432 page ![]() Pinout and Signal Descriptions Signal Descriptions 68HC(9)12D60 — Rev 4.0 Advance Information MOTOROLA Pinout and Signal Descriptions 51 3.5.15 Clock generation module test (CGMTST) The CGMTST pin (PE6) is the output of the clocks tested when CGMTE bit is set in PEAR register. The PIPOE bit must be cleared for the clocks to be tested. Table 3-2. 68HC(9)12D60 Signal Description Summary Pin Name Pin Number Description 80-pin 112-pin EXTAL 35 47 Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. XTAL 36 48 RESET 34 46 An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor causes a reset. ADDR[7:0] DATA[7:0] 23–16 31–24 External bus pins share function with general-purpose I/O ports A and B. In single chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses. ADDR[15:8] DATA[15:8] 48–41 64–57 DBE 25 36 Data bus control and, in expanded mode, enables the drive control of external buses during external reads. ECLK 25 36 Inverted E clock used to latch the address. CAL 25 36 CAL is the output of the Slow Mode programmable clock divider, SLWCLK, and is used as a calibration reference for functions such as time of day. It is overridden when DBE function is enabled. It always has a 50% duty cycle. CGMTST 26 37 Clock generation module test output. MODB/ IPIPE1, MODA/ IPIPE0 26, 27 37, 38 State of mode select pins during reset determine the initial operating mode of the MCU. After reset, MODB and MODA can be configured as instruction queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins. ECLK 28 39 E Clock is the output connection for the external bus clock. ECLK is used as a timing reference and for address demultiplexing. LSTRB/ TAGLO 37 53 Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin function TAGLO used in instruction tagging. See Development Support. R/W 38 54 Indicates direction of data on expansion bus. Shares function with general- purpose I/O. Read/write in expanded modes. IRQ 39 55 Maskable interrupt request input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |