2004 Sep 10

12

Philips Semiconductors

Product specification

Single D-type flip-flop; positive-edge trigger

74LVC1G80

handbook, full pagewidth

MNA653

th

tsu

th

tPHL

tW

tPLH

tsu

1/fmax

VM

VM

VM

VI

GND

VI

GND

CP input

D input

VOH

VOL

Q output

Fig.7

Clock (CP) to output (Q) propagation delays, clock pulse width, D to CP set-up times, the D to CP hold

times and maximum clock pulse frequency.

INPUT

1.65 V to 1.95 V

0.5

≤ 2.0 ns

2.3 V to 2.7 V

0.5

≤ 2.0 ns

2.7 V

1.5 V

2.7 V

≤ 2.5 ns

3.0 V to 3.6 V

1.5 V

2.7 V

≤ 2.5 ns

4.5 V to 5.5 V

0.5

≤ 2.5 ns

The shaded areas indicate when the input is permitted to change for predictable output performance.