DAC8760IPWPR datasheet(33/63 Pages) TI1

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User _ GAIN

CODE _ OUT

CODE •

User _ ZERO

DAC7760, DAC8760

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SBAS528B – JUNE 2013 – REVISED JUNE 2016

Product Folder Links: DAC7760 DAC8760

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where

•

CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01.

•

N is the bits of resolution; 16 for DAC8760 and 12 for DAC7760.

•

User_ZERO is the signed 16-bit code in the zero register.

•

User_GAIN is the unsigned 16-bit code in the gain register.

•

CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for

DAC8760 and 0x000 to 0xFFF for DAC7760).

(6)

This is a purely digital implementation and the output is still limited by the programmed value at both ends of the

voltage or current output range. In addition, remember that the correction only makes sense for endpoints inside

of the true device end points. To correct more than just the actual device error, for example a system offset, the

valid range for the adjustment changes accordingly and must be taken into account. This range is set by the

RANGE, OVR, DUAL OUTEN, and IOUT RANGE bits, as described in Setting Voltage and Current Output

Ranges.

8.3.13 Programmable Slew Rate

The slew rate control feature controls the rate at which the output voltage or current changes. With the slew rate

control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the

attached load.

To reduce the slew rate, enable the slew rate control feature through bit 4 of the Table 17. With this feature

enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate

defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the control register. SRCLK defines the rate at which

the digital slew updates; SRSTEP defines the amount by which the output value changes at each update. If the

DAC data register is read while the DAC output is still changing, the instantaneous value is read. Table 5 lists the

slew rate step-size options. Table 6 summarizes the slew rate update clock options.

Table 5. Slew Rate Step-Size (SRSTEP) Options

SRSTEP

STEP SIZE (LSB)

DAC7760

DAC8760

000

0.0625

001

0.125

010

0.125

011

0.5

100

101

110

111

128

DAC8760IPWPR Datasheet(PDF) 33 Page - Texas Instruments

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