DAC8760IPWPR datasheet(39/63 Pages) TI1

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SDI

LATCH

SCLK

SDI-B

SDI-A

SDI-C

SDO-C

SDO-B

SDO

DAC7760, DAC8760

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SBAS528B – JUNE 2013 – REVISED JUNE 2016

Product Folder Links: DAC7760 DAC8760

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(1)

X denotes don't care bits.

(2)

DAC8760 (16-bit version) shown. DAC7760 (12-bit version) contents are located in DB15:DB4.

For DAC7760, DB3:DB0 are don't care bits when writing and zeros when reading.

(3)

No operation, read operation, and watchdog timer are commands and not registers.

8.5.1.5 Daisy-Chain Operation

For systems that contain multiple DACx760s, use the SDO pin to daisy-chain several devices. This mode is

useful in reducing the number of serial interface lines in applications that use multiple SPI devices. Daisy-chain

mode is enabled by setting the DCEN bit of the control register to 1. By connecting the SDO of the first device to

the SDI input of the next device in the chain, a multiple-device interface is constructed, as Figure 90 illustrates.

Figure 90. Three DACx760s in Daisy-Chain Mode

Like stand-alone operation, the SPI daisy-chain write operation requires one frame, and the read requires two

frames. The rising edge of SCLK that clocks in the MSB of the input frame marks the beginning of the write

cycle. When the serial transfer to all devices is complete, LATCH is taken high. This action transfers the data

from the SPI shift registers to the device internal register of each DACx760 in the daisy-chain. However, the

number of clocks in each frame in this case depends on the number of devices in the daisy chain. For two

devices, each frame is 48 clocks; the first 24 clocks are for the second DAC and the next 24 bits are for the first

DAC. For a readback, the data are read from the two DACs in the following 48-bit frame; the first 24 clocks are

for the second DAC and the next 24 clocks are for the first DAC. The input data to the DACs during the second

frame can be another command or NOP. Similar to the two-device case described, for N devices, each frame is

N × 24 clocks, where N is the total number of DACx760s in the chain.

The serial clock can be a continuous or gated clock. A continuous SCLK source can only be used if LATCH is

taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact

number of clock cycles must be used and LATCH must be taken high after the final clock to latch the data.

8.6 Register Maps

8.6.1 DACx760 Commands and Register Map

Table 16 shows the available commands and registers on the DACx760 devices. No operation, read operation,

and watchdog timer refer to commands and are not explicit registers. For more information on these commands,

see Read Operation and Watchdog Timer. See DACx760 Register Descriptions for descriptions of all DACx760

registers.

Table 16. Command and Register Map

COMMAND

READ/WRITE

ACCESS

DATA BITS (DB15:DB0)

10:9

Control

R/W

CLRSEL

OVR

REXT

OUTEN

SRCLK

SRSTEP

SREN

DCEN

RANGE

Configuration

R/W

(1)

IOUT

RANGE

DUAL

OUTEN

APD

Reser

ved

CALEN

HARTE

CRCEN

WDEN

WDPD

DAC Data

(2)

R/W

D15:D0

No operation

(3)

—

Read Operation

(3)

—

READ ADDRESS

Reset

RESE

Status

Reserved

CRC-

FLT

WD-FLT

I-FLT

SR-

T-FLT

DAC8760IPWPR Datasheet(PDF) 39 Page - Texas Instruments

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