CDCM7005HFGSLASHEM datasheet(21/49 Pages) TI1

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T0064-01

(lockdetect)

SelectedREFatPFD

(clockfedthroughMDividerandMDelay)

VCXO_INatPFD

(clockfedthroughNDividerandNDelay)

T0063-01

PRI_REF

SEC_REF

Internal

ReferenceClock

YxOutput

PRI_SEC_CLK

PrimaryClock

SecondaryClock

PrimaryClock

CDCM7005-SP

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SGLS390G – JULY 2009 – REVISED NOVEMBER 2015

Product Folder Links: CDCM7005-SP

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Feature Description (continued)

Figure 16. Phase Approach of Output to New Reference Clock

9.3.2 PLL Lock for Analog and Digital Detect

The CDCM7005-SP supports two PLL lock indications: the digital lock signal or the analog lock signal. Both

signals indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.

9.3.2.1 PLL Lock/Out-of-Lock Definition

The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD (phase frequency detect) are inside a predefined lock detect

window, or if no cycle-slip appears, for a pre-defined number of successive clock cycles.

The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and

Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window or if a cycle-slip

appears.

Both, the lock detect window and the number of successive clock cycles are user definable (Word 3, Bit 2-6).

Figure 17. Lock Detect Window

The lock detect window describes the maximum allowed time difference for lock detect between the rising edge

of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The

rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock

detect window if there is a phase displacement of more than +0.5 × t(lockdetect) or –0.5 × t(lockdetect).

CDCM7005HFG/EM Datasheet(PDF) 21 Page - Texas Instruments