CDCM7005HFGSLASHEM datasheet(39/49 Pages) TI1

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CDCM7005-SP

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SGLS390G – JULY 2009 – REVISED NOVEMBER 2015

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Application Information (continued)

(1)

Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor. The phase noise measurements were

taken with the CDCM7005-SP EVM and CDCM7005-SP SPI default settings.

(2)

The typical stabilization time is based on the above application example. The stabilization criterion was a stable high level of

PLL_LOCK.

(3)

For further explanations, as well as phase noise/jitter test results using various VCXOs, see application note SCAA067.

10.1.2 Phase Noise Performance

Table 16. Phase Noise Performance

PARAMETER(1)

TEST CONDITIONS

REF_IN PHASE

NOISE

AT 30.72 MHz

VCXO PHASE

NOISE

AT 245.76 MHz

Yx PHASE NOISE

AT 30.72 MHz

UNIT

LVCMOS

LVPECL

TYP(2)

phn10

Phase noise at 10 Hz

Y = 30.72 MHz; ƒPFD = 200

kHz, Loop BW = 20 Hz,

Feedback Divider = 8 × 128

(N × P), ƒREF_IN = 30.72

MHz, M-Divider = 128, ICP =

2 mA

–109

–75

–104

–100

dBc/Hz

phn100

Phase noise at 100 Hz

–125

–97

–116

dBc/Hz

phn1k

Phase noise at 1 kHz

–134

–117

–140

dBc/Hz

phn10k

Phase noise at 10 kHz

–136

–138

–153

–152

dBc/Hz

phn100k

Phase noise at 100 kHz

–138

–148

–156

–153

dBc/Hz

phn1Mk

Phase noise at 1 MHz

–144

–148

–156

–153

dBc/Hz

phn10M

Phase noise at 10 MHz

–144

–148

–156

–153

dBc/Hz

PLL STABILIZATION TIME

tstabi

PLL stabilization time(3)

Y = 30.72 MHz, ƒPFD = 200

kHz, Loop BW = 20 Hz,

Feedback Divider = 8 × 128

(N × P), ƒREF_IN = 30.72

MHz, M-Divider = 128, ICP =

2 mA

400

(1)

The synthesizer phase noise floor can be estimated by measuring the in-band noise at the output of the CDCM7005-SP and subtracting

20log(Feedback Divider) N (in case of CDCM7005-SP it is the N+P divider). The calculated phase noise floor still based on the PFD

update frequency, in the above specification, is 400 kHz.

(2)

The in-band noise can also be normalized to a comparison frequency of 1 Hz. The resulting phase noise floor is: pnfloor =

PNmeasured – 20log(N+P) – 10log(ƒPFD)

where:

pnNfloor = normalized phase noise floor in dBc/Hz

PNmeasured = in-band phase noise measurement in dBc/Hz

20log(N+P) = divider ratio of feedback loop

10log(ƒPFD) = PFD update frequency in Hz

10.1.2.1 In-Band Noise Performance

Table 17. In-Band Noise Performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

pnin-band In-band phase noise test conditions

Y = 900 MHz, ƒPFD = 400 kHz, Loop

BW = 27 kHz, Feedback Divider = 8 × 282

(N × P), ƒREF_IN = 10 MHz; M-Divider = 25,

ICP = 3 mA

–95

dBc/Hz

pnf400

Phase noise floor at 400 kHz ƒPFD, in-band

noise – 20log(feedback div) (1)

–162

dBc/Hz

pnf1

Phase noise floor at 1 Hz ƒPFD, in-band

noise – 20log(feedback div) –

10log(ƒPFD)

(2)

–218

dBc/Hz

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