CDCM7005HFGSLASHEM datasheet(37/49 Pages) TI1

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B0064-01

LO1

(PLL)

16-Bit

DAC

16-Bit

DAC

DAC5687

FIR

DDC

DUC

14-Bit

ADC

ADS5423

3.84MHz

VCXO

491.52MHz

61.44MHz

491.52MHz

122.88MHz

Duplexer

LO1

IF1

LNA

FIR

GC5016

THS4509

TRF3750

(PLL)

TRF3702

CDCM7005

CDCM7005-SP

www.ti.com

SGLS390G – JULY 2009 – REVISED NOVEMBER 2015

Product Folder Links: CDCM7005-SP

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

10.1.1 Clock Generation for Interpolating DACs With the CDCM7005-SP

The CDCM7005-SP, with its specified phase noise performance, is an ideal sampling clock generator for high

speed ADCs and DACs. The CDCM7005-SP is especially of interest for the new high speed DACs, which have

integrated interpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can

typically not be supported from the digital side driving the DAC (for example, DUC, digital up-converter).

Therefore, one approach to interface the DUC to the DAC is the integration of an interpolation filter within the

DAC to reduce the data rate at the digital input of the DAC. In 3G systems, for example, a common sampling

rate of a high speed DAC is 491.52 MSPS. With a four times interpolation of the digital data, the required input

data rate results into 122.88 MSPS, which can be supported easily from the digital side. The DUC GC5016,

which supports up to four WCDMA carriers, provides a maximum output data rate of 150 MSPS. An example is

shown in Figure 25, where the CDCM7005-SP supplies the clock signal for the DUC/DDC and ADC/DAC.

Figure 25. CDCM7005-SP as a Clock Generator for High Speed ADCs and DACs

The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DAC

can be done in different ways. The recommended way is to use the CDCM7005-SP, which generates the fast

sampling clock for the DAC from the data input clock signal. The DAC5687 demands that the edges of the two

input clocks must be phase aligned within ±500 ps for latching the data properly. This phase alignment is well

achieved with the CDCM7005-SP, which assures a maximum skew of 70 ps of the different outputs to each

other.

CDCM7005HFG/EM Datasheet(PDF) 37 Page - Texas Instruments

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