DP83861 datasheet(39/88 Pages) NSC

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nected to the transmit pairs through 150

Ω resistors. Each

receive channel consists of a high precision Analog to Digi-

tal data converter (ADC) which quantizes the incoming

data into a digital word at the rate of 125 Mb/s. The ADC is

sampled with an internal clock of 125 MHz which has been

recovered from the incoming data stream.

The 1000BASE-T transmit section consists of 4 channels,

each transmitting IEEE 802.3ab compliant 17-level PAM-5

data at 125 M symbols/second. The 4 pairs of transmit out-

put pins are AC coupled through the magnetics to the CAT-

5 cable. Each transmit pin pair is serially terminated with 47

Ω resistors to match the cable impedance. Each transmit

channel consists of a Digital to Analog data converter

(DAC) and line driver capable of producing 17 discrete lev-

els corresponding to the PR shaping of a PAM-5 coded

data stream. Each DAC is clocked with an internal 125

MHz clock which is derived from the Ref clock in the MAS-

TER mode of operation, and the recovered receive clock in

the SLAVE mode of operation.

The DP83861 incorporates a sophisticated Phase Genera-

tion Module (PGM) which supports 100/1000 modes of

operation with an external 125 MHz clock reference (

±50

ppm). The PGM module internally generates multiple

phases of clocks at various frequencies to support high

precision and low jitter clocks for robust data recovery, and

to support accurate low jitter transmission of data symbols

in the MASTER and SLAVE mode of operation.

4.8 10BASE-T and 100BASE-TX Transmitter

The 10BASE-T and 100BASE-TX transmitter consists of

several functional blocks which convert synchronous 4-bit

nibble data, as provided by the MII, to a 10 Mb/s MLT sig-

nal for 10BASE-T operation or scrambled MLT-3 125 Mb/s

serial data stream for 100BASE-TX operation. Since the

10BASE-T and 100BASE-TX transmitters are integrated

with the 1000BASE-T, the differential output pins, TD

+/−

are routed to channel A of the AC coupling magnetics.

The block diagram in Figure 10 provides an overview of

each functional block within the 10BASE-T and 100BASE-

TX transmit section.

Figure 10. 100BASE-TX Transmit Block Diagram

4B/5B ENCODER

AND

INJECTION LOGIC

TXDA

TX_CLK

FROM PGM

PARALLEL

TO SERIAL

SCRAMBLER

NRZ-TO-NRZI

BINARY-TO-MLT

DIV-BY-5

100BASE-X

LOOPBACK

NRZ TO

MANCHESTER

DECODER

LINK PULSE

GENERATOR

10/100/1000

DAC/LINE DRIVER

TXD[3:0] / TX_ER

10BASE-T

TXD[3:0] / TX_ER

100BASE-T

DP83861 Datasheet(PDF) 39 Page - National Semiconductor (TI)

DP83861 Datasheet(HTML) 39 Page - National Semiconductor (TI)

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