DP83907VF datasheet(15/70 Pages) NSC

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40 Functional Description (Continued)

FIFO underruns or overruns are caused when a local DMA

request is issued while an ISA bus access is current and the

ISA cycle takes longer to complete than the local DMA’s

tolerable latency This tolerable latency depends on the

FIFO threshold whether it is in byte or word wide mode and

the speed of the DMA clock (BSCLK frequency) Note that

this refers to standard ISA cycles NOT those where the

CHRDY is deasserted extending the cycle

FIFO THRESHOLD DETECTION

To assure that no overwriting of data in the FIFO the FIFO

logic flags a FIFO overrun as the 13th byte is written into the

FIFO effectively shortening the FIFO to 13 bytes The FIFO

logic also operates differently in Byte Mode and in Word

Mode In Byte Mode a threshold is indicated when the na1

byte has entered the FIFO thus with an 8 byte threshold

the DP83907 issues a request to the buffer RAM when the

9th byte has entered the FIFO making the effective thresh-

old 9 bytes For Word Mode the request is not generated

until the na2 bytes have entered the FIFO Thus with a 4

word threshold (equivalent to 8 byte threshold) a request to

the buffer RAM is issued when the 10th byte has entered

the FIFO making the effective threshold 10 bytes

TOLERABLE LATENCY CALCULATION

To prevent a FIFO overrun a byte (or word) of data must be

removed

from the FIFO before the 13th byte is written

Therefore the worst case tolerable latency is the time from

the effective threshold being reached to the time the 13th

byte is written minus the time taken to load the first byte (or

word) of data to the FIFO during a local DMA burst (8

BSCLKs)

tolerable latency e ((overrun b effective) threshold

time to transfer byte on network)

time to fill 1st FIFO location

For the case of a 4 word threshold using a 20 MHz BSCLK

tolerable latency e ((13 b 10) c 800) b (8 c 50) ns

2 ms

To prevent a FIFO underrun a byte (or word) of data must

be added to the FIFO before the last byte is removed

Therefore the worst case tolerable latency is the time from

the effective threshold being reached to the time the last

byte is removed minus the time taken to load the first byte

(or word) of data to the FIFO during a local DMA burst (8

BSCLKs)

tolerable latency e (threshold

time to transfer byte on network)

time to fill 1st FIFO location

For the case of a 4 word threshold using a 20 MHz BSCLK

tolerable latency e (4 c 800) b (8 c 50) ns

28 ms

The worst case latency either overrun or underrun ulti-

mately limits the overall latency that the DP83907 can toler-

ate If the standard ISA cycles are shorter than the worst

case latency then no FIFO overruns or underruns will oc-

cur

BEGINNING OF RECEIVE

At the beginning or reception the DP83907 stores the entire

Address field of each incoming packet in the FIFO to deter-

mine whether the packet matches its Physical Address Reg-

isters or maps to one of its Multicast Registers This causes

the FIFO to accumulate 8 bytes Furthermore there are

some synchronization delays in the DMA PLA Thus the

actual time that a request to access the buffer RAM is as-

serted from the time the Start of Frame Delimiter (SFD) is

detected is 78 ms This operation affects the bus latencies

at 2 and 4 byte thresholds during the first receive request

since the FIFO must be filled to 8 bytes (or 4 words) before

issuing a request to the buffer RAM

END OF RECEIVE

When the end of a packet is detected by the ENDEC mod-

ule the DP83907 enters its end of packet processing se-

quence emptying its FIFO and writing the status information

at the beginning of the 1st buffer The DP83907 holds onto

the memory bus for the entire sequence The longest time

that local DMA will hold the buffer RAM occurs when a

packet ends just as the DP83907 performs its last FIFO

burst The DP83907 in this case performs a programmed

burst transfer followed by flushing the remaining bytes in the

FIFO and completed by writing the header information to

the buffer memory The following steps occur during this

sequence

1 DP83907 issues request to access the RAM because the

FIFO threshold has been reached

2 During the burst the packet ends resulting in the re-

quest being extended

3 DP83907 flushes remaining bytes from FIFO

4 DP83907 performs internal processing to prepare for

writing the header

5 DP83907 writes 4-byte (2-word) header

6 DP83907 de-asserts access to the buffer RAM

BEGINNING OF TRANSMIT

Before transmitting the DP83907 performs a prefetch from

memory to load the FIFO The number of bytes prefetched

is the programmed FIFO threshold The next request to the

buffer RAM is not issued until after the DP83907 actually

begins transmitting data ie after SFD

READING THE FIFO

If the FIFO is read during normal operation the DP83907 will

‘‘hang’’ the ISA bus by deasserting CHRDY and never as-

serting it The FIFO should only be read during loopback

diagnostics

PROTOCOL PLA

The protocol PLA is responsible for implementing the IEEE

8023 protocol including collision recovery with random

backoff The Protocol PLA also formats packets during

transmission and strips preamble and synch during recep-

tion

DMA AND BUFFER CONTROL LOGIC

The DMA and Buffer Control Logic is used to control two

16-bit DMA channels During reception the Local DMA

stores packets in a receive buffer ring located in buffer

memory During transmission the Local DMA uses pro-

grammed pointer and length registers to transfer a packet

from local buffer memory to the FIFO

DP83907VF Datasheet(PDF) 15 Page - National Semiconductor (TI)

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